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| 型号： | AD7884BPZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SAMPLING HS 44-PLCC |
| 标准包装： | 500 |
| 位数： | 16 |
| 采样率（每秒）： | 166k |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 325mW |
| 电压电源： | 双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
REV. E
AD7884/AD7885
–9–
The required 3 V reference is derived from the AD780 and
buffered by the high speed amplifier A3 (AD845, AD817, or
equivalent). A4 is a unity gain inverter that provides the –3 V
negative reference. The gain setting resistors are on-chip and are
factory trimmed to ensure precise tracking of VREF+. Figure 6
shows A3 and A4 as AD845s or AD817s. These have the ability to
respond to the rapidly changing reference input impedance.
CIRCUIT DESCRIPTION
Analog Input Section
The analog input section of the AD7884/AD7885 is shown in
Figure 7. It contains both the input signal conditioning and
sample-and-hold amplifier. Note that the analog input is truly
benign. When SW1A goes open circuit to put the SHA into the
hold mode, SW1B is closed. This means that the input resistors,
R1 and R2, are always connected to either virtual ground or
true ground.
R5
4k
C1
SW1A
A1
3VINF
TO RESIDUE
AMPLIFIER A2
TO 9-BIT
ADC
VREF–
SW1B
R3
3k
R6
2k
R4
4k
R2
5k
R1
3k
3VINS
5VINF
5VINS
A1
Figure 7. AD7884/AD7885 Analog Input Section
When the
± 3V
INS and
± 3V
INF inputs are tied to 0 V, the
input section has a gain of –0.6 and transforms an input signal of
±5 V to the required ±3 V. When the ±5VINS and ±5VINF inputs
are grounded, the input section has a gain of –1 and so the analog
input range is now
±3 V. Resistors R4 and R5, at the amplifier
output, further condition the
±3 V signal to be 0 V to –3 V. This
is the required input for the 9-bit A/D converter section.
With SW1A closed, the output of A1 follows the input (the
sample-and-hold is in the track mode). On the rising edge of
the
CONVST pulse, SW1
A goes open circuit and capacitor C1
holds the voltage on the output of A1. The sample-and-hold is
now in the hold mode. The aperture delay time for the sample-
and-hold is nominally 50 ns.
A/D Converter Section
The AD7884/AD7885 uses a two-pass flash technique in order
to achieve the required speed and resolution. When the
CONVST
control input goes from low to high, the sample-and-hold ampli-
fier goes into the hold mode and a 0 V to –3 V signal is presented
to the input of the 9-bit ADC. The first phase of conversion
generates the 9 MSBs of the 16-bit result and transfers these to
the latch and ALU combination. They are also fed back to the
9 MSBs of the 16-bit DAC. The 7 LSBs of the DAC are
permanently loaded with 0s. The DAC output is subtracted from
the analog input with the result being amplified and offset in the
Residue Amplifier section.
The signal at the output of A2 is proportional to the error
between the first phase result and the actual analog input
signal and is digitized in the second conversion phase. This
second phase begins when the 16-bit DAC and the residue
error amplifier have both settled. First, SW2 is turned off and
SW3 is turned on. Then, the SHA section of the residue
amplifier goes into hold mode. Next SW2 is turned off and
SW3 is turned on. The 9-bit result is transferred to the output
latch and ALU. An error correction algorithm now compensates
for the offset inserted in the residue amplifier section and
errors introduced in the first pass conversion and combines both
results to give the 16-bit answer.
9
VREF–
R4
4k
R5
4k
SW2
SW3
R6
2k
A2
9-BIT
ADC
LATCH
+
ALU
16
0 TO –3V
3V SIGNAL
FROM INPUT
SHA
VREF+F
R7
2k
R8
2k
+3V
–3V
RESIDUE AMP
+ SHA
9
16-BIT
ACCURATE
DAC
VREF+S VINV VREF–
Figure 8. A/D Converter Section
Timing and Control Section
Figure 9 shows the timing and control sequence for the AD7884/
AD7885. When the part receives a
CONVST pulse, the con-
version begins. The input sample-and-hold goes into the hold
mode 50 ns after the rising edge of
CONVST and BUSY goes
low. This is the first phase of conversion and takes 3.35
s to
complete. The second phase of conversion begins when SW2 is
turned off and SW3 is turned on. The residue amplifier and
SHA section (A2 in Figure 8) goes into hold mode at this point
and allows the input sample-and-hold to go back into sample
mode. Thus, while the second phase of conversion is ongoing,
the input sample-and-hold is also acquiring the input signal for
the next conversion. This overlap between conversion and
acquisition allows throughput rates of 166 kSPS to be achieved.
CONVST
BUSY
HOLD
SAMPLE
INPUT
SHA
FIRST PHASE
3.5 s
TACQ
2.5 s
SECOND
PHASE
FIRST PHASE OF CONVERSION
FIRST 9-BIT CONVERSION
DAC SETTLING TIME
RESIDUE AMPLIFIER
SETTLING TIME
SECOND PHASE OF CONVERSION
SECOND 9-BIT CONVERSION
ERROR CORRECTION
OUTPUT LATCH UPDATE
1.8 s
Figure 9. Timing and Control Sequence
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7884BQ | 功能描述:IC ADC 16BIT SAMPLING HS 40-CDIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| AD7885AAP | 制造商:Analog Devices 功能描述:16-Bit, High Speed Sampling ADCs |
| ad7885aap-reel | 制造商:Analog Devices 功能描述: |
| AD7885ABP | 制造商:Rochester Electronics LLC 功能描述:16-BIT,BYTE O/P SAMPL.A/D - Bulk 制造商:Analog Devices 功能描述: |
| AD7885ABP-REEL | 制造商:Analog Devices 功能描述: |
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