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| 型号： | AD7887ARMZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 2CHAN SRL 8MSOP |
| 设计资源： | Software Calibrated, 1 MHz to 8 GHz, 70 dB RF Power Measurement System Using AD8318 (CN0150) |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 125k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 3.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极 |
AD7887
Rev. D | Page 11 of 24
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7887 is a fast, low power, 12-bit, single-supply, single-
channel/dual-channel ADC. The part can be operated from a
3 V (2.7 V to 3.6 V) supply or from a 5 V (4.75 V to 5.25 V) supply.
When operated from either a 5 V or 3 V supply, the AD7887 is
capable of throughput rates of 125 kSPS when provided with a
2 MHz clock.
The AD7887 provides the user with an on-chip, track/hold
analog-to-digital converter reference and a serial interface
housed in an 8-lead package. The serial clock input accesses data
from the part and provides the clock source for the successive
approximation ADC. The part can be configured for single-
channel or dual-channel operation. When configured as a
single-channel part, the analog input range is 0 to VREF (where the
externally applied VREF can be between 1.2 V and VDD). When
the AD7887 is configured for two input channels, the input
range is determined by internal connections to be 0 to VDD.
If single-channel operation is required, the AD7887 can be
operated in a read-only mode by tying the DIN line permanently
to GND. For applications where the user wants to change the
mode of operation or wants to operate the AD7887 as a dual-
channel ADC, the DIN line can be used to clock data into the
part’s control register.
CONVERTER OPERATION
The AD7887 is a successive approximation ADC built around a
schematics of the ADC. Figure 8 shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on AIN.
(REF IN/REF OUT)/2
SAMPLING
CAPACITOR
COMPARATOR
ACQUISITION
PHASE
SW1
A
SW2
AGND
B
AIN
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
06
19
1-
0
08
Figure 8. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 9), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge-redistribution DAC
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 10 shows the ADC transfer function.
(REF IN/REF OUT)/2
SAMPLING
CAPACITOR
COMPARATOR
CONVERSION
PHASE
SW1
A
SW2
AGND
B
VIN
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
06
19
1-
00
9
Figure 9. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7887 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The
ideal transfer characteristic for the AD7887 is shown in Figure
0V
ADC
CO
DE
ANALOG INPUT
111 ... 000
011 ... 111
0.5LSB
+VREF – 1.5LSB
1LSB = VREF/4096
111 ... 111
111 ... 110
000 ... 010
000 ... 001
000 ... 000
06
19
1
-01
0
Figure 10. Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 11 shows a typical connection diagram for the AD7887.
The GND pin is connected to the analog ground plane of the
system. The part is in dual-channel mode so VREF is internally
connected to a well-decoupled VDD pin to provide an analog
input range of 0 V to VDD. The conversion result is output in a
16-bit word with four leading zeros followed by the MSB of the
12-bit result. For applications where power consumption is of
concern, the automatic power-down at the end of conversion
should be used to improve power performance. See the Modes
of Operation section.
DOUT
DIN
SCLK
CS
AIN1
AIN2
GND
0.1F
10F
SUPPLY 2.7V
TO 5.25V
SERIAL
INTERFACE
VDD
AD7887
0V TO VDD
INPUT
C/P
06
19
1-
01
1
Figure 11. Typical Connection Diagram
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