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参数资料
| 型号： | AD7888BR-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/17页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CHAN SRL 16SOIC |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 125k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 3.5mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极 |
AD7888
–13–
SERIAL INTERFACE
Figure 16 shows the detailed timing diagram for serial interfac-
ing to the AD7888. The serial clock provides the conversion
clock and also controls the transfer of information to and from
the AD7888 during conversion.
CS initiates the data transfer and conversion process. For the
autoshutdown mode, the first falling edge of SCLK after the
falling edge of
CS wakes up the part. In all cases, it gates the
serial clock to the AD7888 and puts the on-chip track/hold into
track mode. The input signal is sampled on the second rising
edge of the SCLK input after the falling edge of
CS. Thus, the
first one and one-half clock cycles after the falling edge of
CS is
when the acquisition of the input signal takes place. This time is
denoted as the acquisition time (tACQ). In autoshutdown mode,
the acquisition time must allow for the wake-up time of 5
s. The
on-chip track/hold goes from track mode to hold mode on the
second rising edge of SCLK and a conversion is also initiated on
this edge. The conversion process takes a further fourteen and
one-half SCLK cycles to complete. The rising edge of
CS will
put the bus back into three-state. If
CS is left low a new conver-
sion will be initiated.
The input channel that is sampled is the one selected in the
previous write to the Control Register. Thus, the user must
write ahead of the channel for conversion. In other words, the
user must write the channel address for the next conversion
while the present conversion is in progress.
DONTC
REF
ZERO
ADD2
ADD1
ADD0
PM1
PM0
SCLK
15
6
15
DOUT
DIN
23
4
16
t1
tACQ
tCONVERT
t2
t6
t7
t3
t8
DB11
DB0
DB10
DB9
4 LEADING ZEROS
CS
THREE-
STATE
t4
t5
THREE-
STATE
Figure 16. Serial Interface Timing Diagram
Writing of information to the Control Register takes place on
the first eight rising edges of SCLK in a data transfer. The Con-
trol Register is always written to when a data transfer takes
place. The user must be careful to always set up the correct
information on the DIN line when reading data from the part.
Sixteen serial clock cycles are required to perform the conver-
sion process and to access data from the AD7888. In applica-
tions where the first serial clock edge, following
CS going low, is
a falling edge, this edge clocks out the first leading zero. Thus,
the first rising clock edge on the SCLK clock has the first lead-
ing zero provided. In applications where the first serial clock
edge, following
CS going low, is a rising edge, the first leading
zero may not be set up in time for the processor to read it cor-
rectly. However, subsequent bits are clocked out on the falling
edge of SCLK so they are provided to the processor on the
following rising edge. Thus, the second leading zero is clocked
out on the falling edge subsequent to the first rising edge. The
final bit in the data transfer is valid on the 16th rising edge,
having being clocked out on the previous falling edge.
NOTE: The mark space ratio for SCLK is specified for at least
40% high time (with corresponding 60% low time) or 40% low
time (with corresponding 60% high time). As the SCLK frequency
is reduced, the mark space ratio may vary provided the conver-
sion time never exceeds 50
s—to avoid capacitive droop effects.
REV. C
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