参数资料
| 型号： | AD7893AN-2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL T/H LP 8-DIP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 117k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 45mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极 |
AD7893
–7–
REV. E
Track/Hold Section
The track/hold amplifier on the analog input of the AD7893
allows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-bit accuracy. The input bandwidth of the
track/hold is greater than the Nyquist rate of the ADC, even
when the ADC is operated at its maximum throughput rate of
117 kHz (i.e., the track/hold can handle input frequencies in
excess of 58 kHz).
The track/hold amplifier acquires an input signal to 12-bit accu-
racy in less than 1.5
s. The operation of the track/hold is essen-
tially transparent to the user. The track/hold amplifier goes from
its tracking mode to its hold mode at the start of conversion
(i.e., the rising edge of CONVST). The aperture time for the
track/hold (i.e., the delay time between the external CONVST
signal and the track/hold actually going into hold) is typically
15 ns. At the end of conversion (6
s after the rising edge of
CONVST
) the part returns to its tracking mode. The acquisi-
tion time of the track/hold amplifier begins at this point.
Reference Input
The reference input to the AD7893 is a buffered on-chip with a
maximum reference input current of 1
A. The part is specified
with a +2.5 V reference input voltage. Errors in the reference
source will result in gain errors in the AD7893’s transfer func-
tion and will add to the specified full-scale errors on the part.
On the AD7893-10 it will also result in an offset error injected
in the attenuator stage. Suitable reference sources for the
AD7893 include the AD780 and AD680 precision +2.5 V
references.
Timing and Control Section
Figure 3 shows the timing and control sequence required to ob-
tain optimum performance from the AD7893. In the sequence
shown, conversion is initiated on the rising edge of CONVST,
and new data from this conversion is available in the output reg-
ister of the AD7893 6
s later. Once the read operation has
taken place, a further 600 ns should be allowed before the next
rising edge of CONVST to optimize the settling of the track/
hold amplifier before the next conversion is initiated. With the
serial clock frequency at its maximum of 8.33 MHz, the achiev-
able throughput rate for the part is 6
s (conversion time) plus
1.92
s (read time) plus 0.6 s (acquisition time). This results in
a minimum throughput time of 8.52
s (equivalent to a through-
put rate of 117 kHz).
The read operation consists of sixteen serial clock pulses to the
output shift register of the AD7893. After sixteen serial clock
pulses the shift register is reset and the SDATA line is three-
stated. If there are more serial clock pulses after the sixteenth
clock, the shift register will be moved on past its reset state;
however, the shift register will be reset again on the falling edge
of the CONVST signal to ensure that the part returns to a
known state every conversion cycle. As a result, a read operation
from the output register should not straddle across the falling
edge of CONVST as the output shift register will be reset in the
middle of the read operation, and the data read back into the
microprocessor will appear invalid.
The throughput rate of the part can be increased by reading
data during conversion. If the data is read during conversion,
a throughput time of 6
s (conversion time) plus 1.5 s is
achieved. This minimum throughput time of 7.5
s is achieved
with a slight reduction in performance from the AD7893. The
signal to (noise + distortion) number is likely to degrade by ap-
proximately 1.5 dB while the code flicker from the part will also
increase (see AD7893 PERFORMANCE section).
Because the AD7893 is provided in an 8-pin package to mini-
mize board space, the number of pins available for interfacing is
very limited. As a result, no status signal is provided from the
AD7893 to indicate when conversion is complete. In many
applications, this will not be a problem as the data can be read
from the AD7893 during conversion or after conversion; how-
ever, applications that want to achieve optimum performance
from the AD7893 will have to ensure that the data read does not
occur during conversion or during 600 ns prior to the rising
edge of CONVST. This can be achieved in two ways. The first
is to ensure in software that the read operation is not initiated
until 6
s after the rising edge of CONVST. This will only be
possible if the software knows when the CONVST command is
issued. The second scheme would be to use the CONVST sig-
nal as both the conversion start signal and an interrupt signal.
The simplest way to do this would be to generate a square wave
signal for CONVST with high and low times of 6
s (see Figure
4). Conversion is initiated on the rising edge of CONVST. The
falling edge of CONVST occurs 6
s later and can be used as ei-
ther an active low or falling, edge-triggered interrupt signal to
tell the processor to read the data from the AD7893. Provided
that the read operation is completed 600 ns before the rising
edge of CONVST, the AD7893 will operate to specification.
CONVST
SCLK
CONVERSION IS INITIATED
AND TRACK/HOLD GOES
INTO HOLD
t1
CONVERSION ENDS
6s LATER
SERIAL READ
OPERATION
OUTPUT SERIAL
SHIFT REGISTER IS
RESET
600ns MIN
tCONVERT
READ OPERATION
SHOULD END 600ns
PRIOR TO NEXT
RISING EDGE OF
CONVST
Figure 3. Timing Sequence for Optimum Performance from the AD7893
相关PDF资料 |
PDF描述 |
|---|---|
| MAX3316EEAE+T | IC TXRX RS232 460KBPS 16-SSOP |
| V150B24M150BF3 | CONVERTER MOD DC/DC 24V 150W |
| MS27505E13B35PD | CONN RCPT 22POS BOX MNT W/PINS |
| MS27505E23F35PD | CONN RCPT 100POS BOX MNT W/PINS |
| MS27505E23F35PC | CONN RCPT 100POS BOX MNT W/PINS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7893AN-5 | 功能描述:IC ADC 12BIT SRL T/H LP 8-DIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7893ANZ-10 | 功能描述:IC ADC 12BIT SRL T/H LP 8DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7893ANZ-2 | 功能描述:IC ADC 12BIT SRL T/H LP 8-DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
| AD7893ANZ-5 | 功能描述:IC ADC 12BIT SRL T/H LP 8DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD7893AR-10 | 功能描述:IC ADC 12BIT SRL T/H LP 8-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
发布紧急采购，3分钟左右您将得到回复。