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参数资料
| 型号： | AD7944 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | ADC |
| 英文描述： | 3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| 中文描述： | 3MW的，100ksps的14位ADC的6引脚SOT - 23 |
| 文件页数： | 4/20页 |
| 文件大小： | 480K |
| 代理商： | AD7944 |
AD7940
Rev. 0 | Page 12 of 20
ADC TRANSFER FUNCTION
The output coding of the AD7940 is straight binary. The de-
signed code transitions occur at successive integer LSB values,
i.e., 1 LSB, 2 LSBs. The LSB size is VDD/16384. The ideal transfer
characteristic for the AD7940 is shown in Figure 14.
03305-0-007
000...000
111...111
1 LSB = VDD/16384
1 LSB
+VDD–1 LSB
ANALOG INPUT
0V
000...001
000...010
111...110
111...000
011...111
Figure 14. AD7940 Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 15 shows a typical connection diagram for the AD7940.
VREF is taken internally from VDD and as such should be well
decoupled. This provides an analog input range of 0 V to VDD.
The conversion result is output in a 16-bit word. This 16-bit
data stream consists of two leading zeros, followed by the 14 bits
of conversion data, MSB first. For applications where power
consumption is a concern, the power-down mode should be
used between conversions or bursts of several conversions to
improve power performance (see the Modes of Operation
section).
In fact, because the supply current required by the AD7940 is so
low, a precision reference can be used as the supply source to
the AD7940. For example, a REF19x voltage reference (REF195
for 5 V or REF193 for 3 V) or an AD780 can be used to supply
the required voltage to the ADC (see Figure 15). This configura-
tion is especially useful if the power supply available is quite
noisy, or if the system supply voltages are at some value other
than the required operating voltage of the AD7940, e.g., 15 V.
The REF19x or AD780 will output a steady voltage to the
AD7940. Recommended decoupling capacitors are a 100 nF low
ESR ceramic (Farnell 335-1816) and a 10 F low ESR tantalum
(Farnell 197-130).
03305-
0-
008
AD7940
0V TO VDD
INPUT
VIN
SCLK
SDATA
SERIAL
INTERFACE
C/P
CS
VDD
GND
10
F
TANT
0.1
F
3V
10
F
0.1
F
5V
SUPPLY
REF193
Figure 15. Typical Connection Diagram
Digital Inputs
The digital inputs applied to the AD7940 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digi-
tal inputs applied can go to 7 V and are not restricted by the
VDD + 0.3 V limit as on the analog inputs. For example, if the
AD7940 were operated with a VDD of 3 V, 5 V logic levels could
be used on the digital inputs. However, it is important to note
that the data output on SDATA will still have 3 V logic levels
when VDD = 3 V.
Another advantage of SCLK and CS not being restricted by the
VDD + 0.3 V limit is the fact that power supply sequencing issues
are avoided. If one of these digital inputs is applied before VDD,
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V were applied prior to VDD.
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