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参数资料
| 型号： | AD7946BRMZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 500KSPS 10-MSOP |
| 标准包装： | 1,000 |
| 系列： | PulSAR® |
| 位数： | 14 |
| 采样率（每秒）： | 500k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 19mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | EVAL-AD7946CBZ-ND - BOARD EVALUATION FOR AD7946 |
AD7946
Rev. A | Page 21 of 24
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7946s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7946s is shown in
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO, and the AD7946 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 14 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. The maximum conver-
sion rate may be reduced due to the total readback time. For
instance, with a 3 ns digital host setup time and 3 V interface,
up to four AD7946s running at a conversion rate of 360 kSPS
can be daisy-chained on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
04656-040
CNV
SCK
SDO
SDI
AD7946
B
CNV
SCK
SDO
SDI
AD7946
A
Figure 41. Chain Mode, No BUSY Indicator Connection Diagram
SDOA = SDIB
DA13
DA12
DA11
SCK
1
2
3
262728
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
12
13
tSCK
tSCKL
tSCKH
DA0
15
16
14
SDIA = 0
SDOB
DB13
DB12
DB11
DA1
DB1DB0DA13
DA12
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
04
65
6-
0
41
Figure 42. Chain Mode, No BUSY Indicator Serial Interface Timing
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