参数资料
| 型号： | AD8004ANZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/17页 |
| 文件大小： | 0K |
| 描述： | IC OPAMP CF QUAD LP LDIST 14DIP |
| 标准包装： | 25 |
| 放大器类型： | 电流反馈 |
| 电路数： | 4 |
| 转换速率： | 3000 V/µs |
| -3db带宽： | 250MHz |
| 电流 - 输入偏压： | 40µA |
| 电压 - 输入偏移： | 1000µV |
| 电流 - 电源： | 14mA |
| 电流 - 输出 / 通道： | 50mA |
| 电压 - 电源，单路/双路(±)： | 4 V ~ 12 V，±2 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 14-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 14-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 769 (CN2011-ZH PDF) |
REV. C
AD8004
–12–
Table I. Recommended Component Values
1 and Typical Bandwidths
Alternate
Gain
–10
–2
–1
+1
+2
+10
AD8004 (DIP)
PACKAGE TYPE
RF (
)
499
698
499
649
499
1.21 k
806
1.10 k
698
499
RG (
)
49.9
348
249
649
499
1.10 k
698
54.9
RT
2 (
)
None
57.6
61.9
53.6
54.9
50
Small Signal BW
@
±5 V
S (MHz)
155
125
180
135
190
150
250
115
185
135
Peaking @
±5 V
S
< 0.3 dB
None
0.3 dB
None
0.3 dB
1.3 dB
1.7 dB
< 0.14 dB
0.4 dB
< 0.3 dB
0.1 dB Flatness
@
±5 V
S (MHz)
25
30
35
Small Signal BW
@ +5 VS (MHz)
135
105
155
120
160
130
200
95
150
120
AD8004 (SOIC)
PACKAGE TYPE
RF (
)
499
698
499
750
499
1.10 k
698
1.10 k
604
499
RG (
)
49.9
348
249
750
499
1.10 k
604
54.9
RT
2 (
)
None
57.6
61.9
53.6
54.9
50
Small Signal BW
@
±5 V
S (MHz)
155
130
190
125
195
150
225
110
175
135
Peaking @
±5 V
S
< 0.7 dB
< 0.1 dB
0.5 dB
None
0.4 dB
1.3 dB
1.8 dB
< 0.1 dB
0.5 dB
< 0.2 dB
0.1 dB Flatness
@
±5 V
S (MHz)
35
25
30
Small Signal BW
@ +5 VS (MHz)
135
115
175
110
165
130
195
95
155
120
NOTES
1Resistor values listed are standard 1% tolerance.
2R
T chosen for 50
characteristic input impedance.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
ground path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see
Figure 13). One end should be connected to the ground plane and
the other within 1/8" of each power pin. An additional (4.7
F to
10
F) tantalum electrolytic capacitor should be connected in
parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains. An example of extra inverting input
capacitance can be seen on the plot of Figure 10.
Stripline design techniques should be used for long signal traces
(greater than about 1"). These should be designed with the
proper system characteristic impedance and be properly termi-
nated at each end.
NONINVERTING CONFIGURATION
C1
0.1 F
C2
0.1 F
C4
10 F
C3
10 F
RT
VIN
VOUT
+VS
–VS
RG
RF
RBT, 50
1/4
C1
0.1 F
C2
0.1 F
C4
10 F
C3
10 F
RT
VIN
VOUT
+VS
–VS
RG
RF
RBT, 50
1/4
INVERTING CONFIGURATION
Figure 13. Inverting and Noninverting Configurations
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