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| 型号： | AD8039ART-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC OPAMP VF DUAL LP LN SOT23-8 |
| 标准包装： | 1 |
| 放大器类型： | 电压反馈 |
| 电路数： | 2 |
| 转换速率： | 425 V/µs |
| -3db带宽： | 350MHz |
| 电流 - 输入偏压： | 400pA |
| 电压 - 输入偏移： | 500µV |
| 电流 - 电源： | 1mA |
| 电压 - 电源，单路/双路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 |
| 供应商设备封装： | SOT-23-8 |
| 包装： | 标准包装 |
| 其它名称： | AD8039ART-REEL7DKR |
AD8038/AD8039
Rev. G | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
12.6 V
Power Dissipation
See Figure 5
Common-Mode Input Voltage
±VS
Differential Input Voltage
±4 V
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +85°C
Lead Temperature (Soldering, 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8038/AD8039
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8038/AD8039.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent power
is the voltage between the supply pins (VS) multiplied by the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, then the total drive power is VS/2 × IOUT, some of which
is dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = quiescent power + (total drive power load power)
PD = [VS × IS] + [(VS/2) × (VOUT/RL)] [VOUT2/RL]
AMBIENT TEMPERATURE (°C)
0
–55
MA
XI
MU
M
P
O
W
E
R
D
IS
S
IPA
T
IO
N
(W
)
1.0
–25
5
35
65
95
125
1.5
2.0
SOIC-8
0.5
SC70-5
SOT-23-8
02
95
1-
00
5
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
RMS output voltages should be considered. If RL is referenced to
VS, as in single-supply operation, then the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS /4 for RL to midsupply
PD = (VS × IS) + (VS/4)2/RL
In single-supply operation with RL referenced to VS, worst case
is VOUT = VS /2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, throughholes, ground, and power planes reduce
the θJA. Care must be taken to minimize parasitic capacitances at
the input leads of high speed op amps as discussed in the
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W), 5-lead SC70 (210°C/W), and 8-lead SOT-23
(160°C/W) packages on a JEDEC standard 4-layer board.
θJA values are approximations.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current
from the AD8038/AD8039 will likely cause a catastrophic failure.
ESD CAUTION
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