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| 型号： | AD8045ARDZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/25页 |
| 文件大小： | 0K |
| 描述： | IC OPAMP VF ULDIST LN 70MA 8SOIC |
| 产品培训模块： | Practical Guide High Speed PCB Layout |
| 标准包装： | 1,000 |
| 放大器类型： | 电压反馈 |
| 电路数： | 1 |
| 转换速率： | 1350 V/µs |
| -3db带宽： | 1GHz |
| 电流 - 输入偏压： | 2µA |
| 电压 - 输入偏移： | 200µV |
| 电流 - 电源： | 16mA |
| 电流 - 输出 / 通道： | 70mA |
| 电压 - 电源，单路/双路(±)： | 3.3 V ~ 12 V，±1.65 V ~ 6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 供应商设备封装： | 8-SOIC-EP |
| 包装： | 带卷 (TR) |
AD8045
Rev. A | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
12.6 V
Power Dissipation
See Figure 4
Common-Mode Input Voltage
VS 0.7 V to +VS + 0.7 V
Differential Input Voltage
±V
S
Exposed Paddle Voltage
VS
Storage Temperature
65°C to +125°C
Operating Temperature Range
40°C to +125°C
Lead Temperature Range
(Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, i.e., θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
SOIC
80
30
°C/W
LFCSP
93
35
°C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8045 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric perform-
ance of the AD8045. Exceeding a junction temperature of
175°C for an extended period of time can result in changes in
silicon devices, potentially causing degradation or loss of
functionality.
The power dissipated in the package (PD) is the sum of the qui-
escent power dissipation and the power dissipated in the die
due to the AD8045 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
PD = Quiescent Power + (Total Drive Power – Load Power)
()
L
2
OUT
L
OUT
S
D
R
V
–
R
V
2
V
I
V
P
×
+
×
=
RMS output voltages should be considered. If
RL is referenced to
VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when
VOUT = VS/4 for RL to midsupply.
() (
)
L
S
D
R
/
V
I
V
P
2
4
+
×
=
In single-supply operation with RL referenced to VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduce θJA.
Figure 4 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
04814-0-080
AMBIENT TEMPERATURE (°C)
120
–40
–20
0
20
40
60
80
100
M
A
XIM
U
M
POW
E
R
D
ISSIPA
TION
(
W
at
ts
)
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LFCSP
SOIC
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
and loss of functionality.
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