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| 型号： | AD8079BR-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/12页 |
| 文件大小： | 0K |
| 描述： | IC AMP BUF DUAL LP LDIST 8SOIC |
| 标准包装： | 1,000 |
| 放大器类型： | 缓冲器 |
| 电路数： | 2 |
| 转换速率： | 800 V/µs |
| -3db带宽： | 260MHz |
| 电流 - 输入偏压： | 3µA |
| 电压 - 输入偏移： | 10000µV |
| 电流 - 电源： | 10mA |
| 电流 - 输出 / 通道： | 70mA |
| 电压 - 电源，单路/双路(±)： | 6 V ~ 12 V，±3 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
9
REV. A
AD8079
–9–
The current feedback nature of the op amps, in addition to
enabling the wide bandwidth, provides an output drive of more
than 3 V p-p into a 20
load for each output at 20 MHz. On
the other hand, the voltage feedback nature provides symmetri-
cal high impedance inputs and allows the use of reactive compo-
nents in the feedback network.
The circuit consists of the two op amps each configured as a
unity gain follower by the 750
feedback resistors between
each op amp’s output and inverting input. The output of each
op amp has a 750
resistor to the inverting input of the other
op amp. Thus, each output drives the other op amp through a
unity gain inverter configuration. By connecting the two ampli-
fiers as cross-coupled inverters, their outputs are free to be equal
and opposite, assuring zero-output common-mode voltage.
With this circuit configuration, the common-mode signal of the
outputs is reduced. If one output moves slightly higher, the
negative input to the other op amp drives its output to go
slightly lower and thus preserves the symmetry of the comple-
mentary outputs which reduces the common-mode signal.
The resulting architecture offers several advantages. First, the
gain can be changed by changing a single resistor. Changing
either RF or RG will change the gain as in an inverting op amp
circuit. For most types of differential circuits, more than one
resistor must be changed to change gain and still maintain good
CMR.
Reactive elements can be used in the feedback network. This is
in contrast to current feedback amplifiers that restrict the use of
reactive elements in the feedback. The circuit described requires
about 1.3 pF of capacitance in shunt across RF in order to opti-
mize peaking and realize a –3 dB bandwidth of more than
110 MHz.
The peaking exhibited by the circuit is very sensitive to the
value of this capacitor. Parasitics in the board layout on the or-
der of tenths of picofarads will influence the frequency response
and the value required for the feedback capacitor, so a good lay-
out is essential.
The shunt capacitor type selection is also critical. Good micro-
wave type chip capacitors with high Q were found to yield best
performance.
FREQUENCY – Hz
0.1M
1G
1M
10M
100M
CC = 1.3pF
VIN = 10dBm
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
OUTPUT
–
dB
OUT+
OUT–
Figure 28. Differential Driver Frequency Response
Layout Considerations
The specified high speed performance of the AD8079 requires
careful attention to board layout and component selection.
Proper RF design techniques and low parasitic component se-
lection are mandatory.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Figure
29). One end should be connected to the ground plane and the
other within 1/8 in. of each power pin. An additional large
(4.7
F–10 F) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with a
characteristic impedance of 50
or 75 and be properly termi-
nated at each end.
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