参数资料
| 型号： | AD808-622BR |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC FIBER OPTIC RCVR 16-SOIC |
| 标准包装： | 1 |
| 类型： | 接收器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
AD808–SPECIFICATIONS
REV. 0
–2–
Parameter
Condition
Min
Typ
Max
Units
QUANTIZER–DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN
2.5
VS
V
Input Sensitivity, VSENSE
PIN–NIN, Figure 1, BER = ≤ 1 × 10
–10
10
4.0
mV
Input Overdrive, VOD
Figure 1, BER =
≤ 1 × 10–10
5
2.0
mV
Input Offset Voltage
1.0
mV
Input Current
10
A
Input RMS Noise
BER =
≤ 1 × 10–10
100
V
Input Peak-to-Peak Noise
BER =
≤ 1 × 10–10
1.5
mV
QUANTIZER–AC CHARACTERISTICS
Upper –3 dB Bandwidth
600
800
MHz
Input Resistance
10
k
Input Capacitance
2pF
Pulsewidth Distortion
50
ps
LEVEL DETECT
Level Detect Range
RTHRESH = 22.1 k
6.5
10
13.5
mV
RTHRESH = 6.98 k
13
18
23
mV
RTHRESH = 0
28.5
40
45.5
mV
Response Time
DC Coupled
0.1
1.5
s
Hysteresis (Electrical)
RTHRESH = 22.1 k (See Figure 8)
5
9.0
dB
RTHRESH = 6.98 k
3.0
5.1
9.0
dB
RTHRESH = 0
3.0
7.0
10.0
dB
SDOUT Output Logic High
Load = +3.2 mA
4.0
4.7
V
SDOUT Output Logic Low
Load = –3.2 mA
0.2
0.4
V
PHASE-LOCKED LOOP NOMINAL
CENTER FREQUENCY
622.08
MHz
CAPTURE RANGE
620
624
MHz
TRACKING RANGE
620
624
MHz
STATIC PHASE ERROR (See Figure 7)
2
7–1 PRN Sequence
22
81
Degrees
SETUP TIME (tSU)
Figure 2
550
900
ps
HOLD TIME (tH)
Figure 2
700
1050
ps
PHASE DRIFT
240 Bits, No Transitions
50
Degrees
JITTER
2
7–1 PRN Sequence
2.5
3.6
Degrees rms
2
23–1 PRN Sequence
2.5
3.6
Degrees rms
JITTER TOLERANCE
f = 30 Hz
3000
Unit Intervals
f = 300 Hz
24
300
Unit Intervals
f = 25 kHz
1.7
3.7
Unit Intervals
f = 250 kHz
0.28
0.56
Unit Intervals
f = 5 MHz
0.18
0.45
Unit Intervals
JITTER TRANSFER
Peaking (Figure 14)
CD = 0.47 F
0.04
dB
Bandwidth
333
450
kHz
Acquisition Time
CD = 0.1 F2
23–1 PRN Sequence, T
A = +25°C2 × 10
6
3
× 106
Bit Periods
CD = 0.47 FVCC = 5 V, VEE = GND
8
× 106
12
× 106 Bit Periods
POWER SUPPLY VOLTAGE
VMIN to VMAX
4.5
5.5
Volts
POWER SUPPLY CURRENT
VCC = 5.0 V, VEE = GND,
TA = +25°C
55
80
100
mA
PECL OUTPUT VOLTAGE LEVELS
Output Logic High, VOH
TA = +25°C
–1.2
–1.0
–0.7
Volts
Output Logic Low, VOL
Referenced to VCC
–2.2
–2.0
–1.7
Volts
SYMMETRY (Duty Cycle)
ρ = 1/2, T
A = +25°C,
Recovered Clock Output, Pin 5
VCC = 5 V, VEE = GND
45
55
%
OUTPUT RISE / FALL TIMES
Rise Time (tR)
20%–80%
174
350
500
ps
Fall Time (tF)
80%–20%
136
315
500
ps
CLOCK SKEW (tRCS)
Positive Number Indicates Clock
Leading Data
–100
130
250
ps
Specifications subject to change without notice.
(TA = TMIN to TMAX, VS = VMIN to VMAX, CD = 0.47 F, unless otherwise noted)
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