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参数资料
| 型号： | AD808-622BRZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC RECEIVER FIBER OPTIC 16SOIC |
| 标准包装： | 1,000 |
| 类型： | 接收器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
AD808
REV. 0
–5–
Damping Factor,
ζ
Damping factor,
ζ describes the compensation of the second
order PLL. A larger value of
ζ corresponds to more damping
and less peaking in the jitter transfer function.
Acquisition Time
This is the transient time, measured in bit periods, required for
the AD808 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100
× on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
BINARY
OUTPUT
SCOPE
PROBE
AD808 QUANTIZER
VCM
4mVp-p
INPUT
a. Single-Ended Input Application
BINARY
OUTPUT
SCOPE
PROBE
AD808 QUANTIZER
VCM
2mVp-p
+INPUT
–INPUT
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
500
5k
AVEE
AVCC
OUT
PIN
NIN
a. Quantizer Differential Input Stage
6k
THRADJ
AVEE
80k
1.2V +VBE
b. Threshold Adjust
30
VCC1
SDOUT
VEE
IOL
IOH
30
c. Signal Detect Output (SDOUT)
140
VCC2
DIFFERENTIAL
OUTPUT
VEE
7.8mA
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 4. (a–d) Simplified Schematics
The AD808 has internal circuits to set the common-mode volt-
age at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as
shown in Figure 4a. This allows very simple capacitive coupling
of the signal from the preamp in the AD808 as shown in Figure
3. The internal common-mode potential is a diode drop (ap-
proximately 0.8 V) below the positive supply as shown in Figure
4a. Since the common mode is referred to the positive supply, it
is useful to bypass the common mode of the preamp to the
positive supply as well, if this is an option. Note, it is not neces-
sary to use capacitive coupling of the input signal with the
AD808. Figure 14 shows the input common-mode voltage can
be externally set.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD808ACHIPS | 功能描述:Receiver Die 制造商:analog devices inc. 系列:- 包装:- 零件状态:上次购买时间 类型:接收器 协议:- 驱动器/接收器数:- 双工:- 接收器滞后:- 数据速率:- 电压 - 电源:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:- 供应商器件封装:模具 标准包装:1 |
| AD8091AR | 制造商:Analog Devices 功能描述:OP Amp Single GP R-R O/P 制造商:Rochester Electronics LLC 功能描述:LOW COST RAIL TO RAIL OUT AMPLIFIER - Bulk 制造商:Analog Devices 功能描述:IC SM AMP HIGH SPEED RRO/P |
| AD8091AR-EBZ | 功能描述:BOARD EVAL FOR AD8091AR RoHS:是 类别:编程器，开发系统 >> 评估板 - 运算放大器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- |
| AD8091AR-REEL | 制造商:Analog Devices 功能描述:OP Amp Single GP R-R O/P 制造商:Rochester Electronics LLC 功能描述:LOW COST RAIL-TO-RAIL OUTPUT AMPLIFIER - Tape and Reel |
| AD8091AR-REEL7 | 制造商:Analog Devices 功能描述:OP Amp Single GP R-R O/P 制造商:Rochester Electronics LLC 功能描述:LOW COST RAIL-TO-RAIL OUTPUT AMPLIFIER - Tape and Reel |
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