参数资料
| 型号： | AD810ANZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC CURR-FDBK AMP VIDEO LP 8-DIP |
| 标准包装： | 50 |
| 应用： | 电流反馈 |
| 电路数： | 1 |
| -3db带宽： | 80MHz |
| 转换速率： | 1000 V/µs |
| 电流 - 电源： | 6.8mA |
| 电流 - 输出 / 通道： | 60mA |
| 电压 - 电源，单路/双路(±)： | 5 V ~ 36 V，±2.5 V ~ 18 V |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 768 (CN2011-ZH PDF) |
AD810
REV. A
–13–
of the disable the disable pin for
±5 V supplies. If driven by
complementary output CMOS logic (such as the 74HC04), the
disable time (until the output goes high impedance) is about
100 ns and the enable time (to low impedance output) is about
170 ns on
±5 V supplies. The enable time can be extended to
about 750 ns by using open drain logic such as the 74HC05.
When operated on
±15 V supplies, the AD810 disable pin may
be driven by open drain logic such as the 74C906. In this case,
adding a 10 k
pull-up resistor from the disable pin to the plus
supply will decrease the enable time to about 150 ns. If there is
a nonzero voltage present on the amplifier's output at the time it
is switched to the disabled state, some additional decay time will
be required for the output voltage to relax to zero. The total
time for the output to go to zero will generally be about 250 ns
and is somewhat dependent on the load impedance.
OPERATION AS A VIDEO LINE DRIVER
The AD810 is designed to offer outstanding performance at
closed-loop gains of one or greater. At a gain of 2, the AD810
makes an excellent video line driver. The low differential gain
and phase errors and wide –0.1 dB bandwidth are nearly
independent of supply voltage and load (as seen in Figures 49
and 50).
AD810
75
7
3
2
3
0.1F
+VS
6
–VS
4
0.1F
VIN
VOUT
715
75
CABLE
75
75
75
CABLE
715
Figure 47. A Video Line Driver Operating at a Gain of +2
GAIN = +2
RL = 150
±2.5V
VS = ±15V
±5V
±2.5V
PHASE
GAIN
0
–5
10
100
–1
–2
–3
–4
1
1000
0
–45
–90
–135
–180
–225
–270
CLOSED-LOOP
GAIN
–
dB
PHASE
SHIFT
–
Degrees
FREQUENCY – MHz
±5V
VS = ±15V
Figure 48. Closed-Loop Gain and Phase vs. Frequency,
G = +2, RL = 150, RF = 715
0.10
0
15
0.03
0.01
6
0.02
5
0.06
0.04
0.05
0.07
0.08
0.09
14
13
12
11
10
9
8
7
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
GAIN
PHASE
GAIN = +2
RF = 715
RL = 150
fC = 3.58MHz
100 IRE
MODULATED RAMP
SUPPLY VOLTAGE – ± Volts
DIFFERENTIAL
GAIN
–
%
DIFFERENTIAL
PHASE
–
Degrees
Figure 49. Differential Gain and Phase vs. Supply Voltage
100k
1M
100M
10M
+0.1
0
–0.1
0
+0.1
NORMALIZED
GAIN
–
dB
FREQUENCY – Hz
RL = 150
RL= 1k
±15V
±5V
±15V
±5V
±2.5
Figure 50. Fine-Scale Gain (Normalized) vs. Frequency
for Various Supply Voltages, Gain = +2, RF = 715
110
40
20
2
30
70
50
60
80
90
100
18
16
14
12
10
8
6
4
–3dB
BANDWIDTH
–
MHz
SUPPLY VOLTAGE - ±Volts
PEAKING
1.0dB
PEAKING
0.1dB
G = +2
RL = 150
VO = 250mV p-p
RF = 500
RF = 750
RF = 1k
≤
Figure 51. –3 dB Bandwidth vs. Supply Voltage,
Gain = +2, RL = 150
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