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| 型号： | AD8120ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/16页 |
| 文件大小： | 0K |
| 描述： | IC ANLG VIDEO DELAY LINE 32LFCSP |
| 标准包装： | 5,000 |
| 类型： | 视频延迟线 |
| 应用： | HD 视频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-EP（5x5） |
| 包装： | 带卷 (TR) |
AD8120
Data Sheet
Rev. A | Page 10 of 16
ANALOG CONTROL
A number of video transmission systems do not have a microcon-
troller embedded or otherwise available to provide digital control.
These systems require analog control. Potentiometer control is
one of the most common ways to implement analog control (see
Figure 25). To select analog control, set the MODE pin high.
The AD8120 has one analog control input for each channel: VCR,
VCG, and VCB. The maximum recommended control voltage range
on these inputs is 0 V to 2.0 V, although the actual control range
where delay changes take effect is smaller and lies within this larger
range. An internal ADC converts the analog control voltages
into binary delay codes; therefore, the analog control is discrete
with nominally 0.8 ns resolution. Figure 6 illustrates the typical
transfer characteristic between control voltage and delay code.
POWER DOWN
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. Note that
the input high level for the power-down input is higher than it
is for the other digital inputs. Refer to the Specifications in
Table 1 for details.
DIGITAL CONTROL
Set the MODE pin low to select digital control (SPI or I2C). Set
the SER_SEL pin high to select SPI mode, or set the SER_SEL
reading and writing the red, green, and blue registers.
Table 6. Read/Write Instruction and Color Registers
Operation
R/W Bit
C1 Bit
C0 Bit
Write Red
0
Read Red
1
0
Write Green
0
1
Read Green
1
0
1
Write Blue
0
1
0
Read Blue
1
0
SPI Control
The SPI bus operates in full-duplex mode and consists of four
digital lines: SDI, SDO, SCK, and CS.
Table 7. AD8120 SPI Pin Descriptions
Pin No.
Pin
Name
Description
29
SDI
Serial data input, master out slave in (MOSI)
2
SDO
Serial data output, master in slave out (MISO)
30
SCK
Serial clock from master
31
CS
Chip select; active low
The AD8120 is programmed in SPI mode using a 2-byte sequence
(see Table 8). Data is clocked into the SDI pin or clocked out of
the SDO pin on the rising edge of the clock, MSB first. The first
byte contains the read/write (R/W) instruction and the color reg-
ister address (see Table 6). The second byte contains the delay
code to write to the part (R/W = 0) or the stored delay code to
read from the part (R/W = 1).
Figure 17 shows how to write Delay Code 42 to the green
register. Figure 18 shows how to read Delay Code 21 from
the blue register.
Table 8. SPI 2-Byte Sequence
Byte 1 (R/W Bit and Color Register)
Byte 2 (Data)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDI
R/W
0
C1
C0
X
D5
D4
D3
D2
D1
D0
SDO
X
D5
D4
D3
D2
D1
D0
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