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参数资料
| 型号： | AD8224HBCPZ-WP |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC AMP INST DUAL PREC LN 16LFCSP |
| 标准包装： | 64 |
| 放大器类型： | 仪表 |
| 电路数： | 2 |
| 输出类型： | 满摆幅 |
| 转换速率： | 2 V/µs |
| -3db带宽： | 1.5MHz |
| 电流 - 输入偏压： | 10pA |
| 电压 - 输入偏移： | 175µV |
| 电流 - 电源： | 750µA |
| 电流 - 输出 / 通道： | 15mA |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 36 V，±2.25 V ~ 18 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN，CSP |
| 供应商设备封装： | 16-LFCSP（4x4） |
| 包装： | 托盘 - 晶粒 |
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Data Sheet
AD8224
Rev. C | Page 21 of 28
Table 12. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG ()
Calculated Gain
49.9 k
1.990
12.4 k
4.984
5.49 k
9.998
2.61 k
19.93
1.00 k
50.40
499
100.0
249
199.4
100
495.0
49.9
991.0
The AD8224 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8224 specifications to determine the total gain
accuracy of the system. When the gain resistor is not used,
gain error and gain drift are kept to a minimum.
REFERENCE TERMINAL
The output voltage of the AD8224 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF1 pin or the
REF2 pin to level-shift the output so that the AD8224 can drive
a single-supply ADC. Pin REFx is protected with ESD diodes
and should not exceed either +VS or VS by more than 0.5 V.
For best performance, source impedance to the REF terminal
should be kept below 1 . As shown in Figure 55, the reference
terminal, REF, is at one end of a 20 kΩ resistor. Additional
impedance at the REF terminal adds to this 20 kΩ resistor and
results in amplification of the signal connected to the positive
input. The amplification from the additional RREF can be
computed by
(
)
REF
R
+
kΩ
40
kΩ
20
2
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the CMRR of
the amplifier.
INCORRECT
AD8224
VREF
CORRECT
AD8224
OP2177
+
–
VREF
CORRECT
AD8224
+
–
VREF
06286-
058
Figure 56. Driving the Reference Pin
LAYOUT
The AD8224 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout. The AD8224 pinout is arranged in a logical
manner to aid in this task.
Package Considerations
The AD8224 is available in two version s of the 16-lead, 4 mm ×
4 mm LFCSP package: with or without an exposed paddle. Blindly
copying the footprint from another 4 mm × 4 mm LFCSP part
is not recommended because it may not have the same thermal
pad size and leads. Refer to the Outline Dimensions section to
verify that the PCB symbol has the correct dimensions.
Hidden Paddle Package
The AD8224 is available in an LFCSP package with a hidden
paddle. It is the preferred package for the AD8224. Unlike
chip scale packages where the pad limits routing capability,
this package allows routes and vias directly underneath the
chip, so that the full space savings of the small LFCSP can be
realized. Although the package has no metal in the center of
the part, the manufacturing process does leave a very small
section of exposed metal at each of the package corners, shown
section. This metal is connected to +VS through the part.
Because of a possibility of a short, vias should not be placed
underneath these exposed metal tabs.
06286-
101
HIDDEN
PADDLE
BOTTOM VIEW
EXPOSED LEAD
FRAME TABS
NOTES
1. EXPOSED LEAD FRAME TABS AT THE FOUR CORNERS
OF THE PACKAGE ARE INTERNALLY CONNECTED TO
+VS. REFER TO THE OUTLINE DIMENSIONS PAGE, FOR
FURTHER INFORMATION ON PACKAGE AVAILABILITY.
Figure 57. Hidden Paddle Package: Bottom View
Exposed Paddle Package
The AD8224 4 mm × 4 mm LFCSP is also available with an
exposed thermal paddle package version. This pad is connected
internally to +VS. The pad can either be left unconnected or
connected to the positive supply rail. Space between the leads
and thermal pad should be kept as wide as possible for the best
bias current performance. To maintain the AD8224 ultralow
bias current performance, the thermal pad area can be reduced
to extend the gap between the leads and the pad. The exposed
paddle package also has exposed lead frame tabs at the corners
of the package, similar to those of the hidden paddle package,
which are internally connected to +VS. Do not place vias
underneath these metal tabs.
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