参数资料
型号: AD823AR-REEL
厂商: ANALOG DEVICES INC
元件分类: 运动控制电子
英文描述: RECTIFIER SCHOTTKY SINGLE 8A 30V 200A-ifsm 0.55V-vf 0.5mA-ir TO220AC 50/TUBE
中文描述: DUAL OP-AMP, 3500 uV OFFSET-MAX, PDSO8
封装: PLASTIC, MS-012AA, SOIC-8
文件页数: 11/16页
文件大小: 439K
代理商: AD823AR-REEL
AD823
REV. 0
–11–
THEORY OF OPERATION
This AD823 is fabricated on Analog Devices’ proprietary
complementary bipolar (CB) process that enables the construc-
tion of pnp and npn transistors with similar f
T
s in the 600 MHz
to 800 MHz region. In addition, the process also features
N-channel JFETs, which are used in the input stage of the AD823.
These process features allow the construction of high frequency,
low distortion op amps with picoampere input currents. This
design uses a differential-output input stage to maximize band-
width and headroom (see Figure 35). The smaller signal swings
required on the S1P, S1N outputs reduce the effect of nonlinear
currents due to junction capacitances and improve the distortion
performance. With this design harmonic distortion of better
than –91 dB @ 20 kHz into 600
with V
OUT
= 4 V p-p on a
single 5 volt supply is achieved. The complementary common-
emitter design of the output stage provides excellent load drive
without the need for emitter followers, thereby improving the
output range of the device considerably with respect to conven-
tional op amps. The AD823 can drive 20 mA with the outputs
within 0.6 V of the supply rails. The AD823 also offers out-
standing precision for a high speed op amp. Input offset voltages
of 1 mV max and offset drift of 2
μ
V/
°
C are achieved through
the use of Analog Devices’ advanced thin-film trimming
techniques.
A “Nested Integrator” topology is used in the AD823 (see small-
signal schematic shown in Figure 36). The output stage can be
modeled as an ideal op amp with a single-pole response and a
unity-gain frequency set by transconductance g
m2
and capacitor
C2. R1 is the output resistance of the input stage; g
m
is the in-
put transconductance. C1 and C5 provide Miller compensation
for the overall op amp. The unity gain frequency will occur at
g
m
/C5. Solving the node equations for this circuit yields:
V
OUT
Vi
=
A
0
(
sR
1[
C
1(
A
2
+
1)]
+
1)
×
s
g
m
2
C
2
+
1
where:
A
0 = g
m
g
m2
R2R1 (Open Loop Gain of Op Amp)
A
2 = g
m2
R2 (Open Loop Gain of Output Stage)
V
CC
V
INP
V
INN
V
EE
R42
R37
J1
J6
I1
C6
R33
I2
R43
I3
Q56
S1P
Q72
Q61
Q46
I5
V
BE
+ 0.3V
S1N
Q53
Q35
Q48
V
CC
Q21
Q62
Q60
Q54
R44
R28
Q52
I4
Q59
A=1
V
B
C1
Q17
A=19
V
OUT
C2
Q18
Q49
Q55
Q43
I6
Q44
A=1
Q57
A=19
Q58
V1
Figure 35. Simplified Schematic
10V
–10V
R
L
= 100k
C
L
= 50pF
500ns
5V
Figure 34. Pulse Response, V
S
=
±
15 V, G = +1
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