参数资料
| 型号： | AD8307ARZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC AMP LOGARITHMIC 8SOIC |
| 标准包装： | 2,500 |
| 类型： | 对数放大器 |
| 应用： | 接收器信号强度指示（RSSI） |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 带卷 (TR) |
AD8307
Rev. D | Page 3 of 24
SPECIFICATIONS
VS = 5 V, TA = 25°C, RL ≥ 1 MΩ, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
GENERAL CHARACTERISTICS
Input Range (±3 dB Error)
From noise floor to maximum input
92
dB
Input Range (±1 dB Error)
From noise floor to maximum input
88
dB
Logarithmic Conformance
f ≤ 100 MHz, central 80 dB
±0.3
±1
dB
f = 500 MHz, central 75 dB
±0.5
dB
Logarithmic Slope
23
25
27
mV/dB
vs. Temperature
23
27
mV/dB
Logarithmic Intercept
Sine amplitude, unadjusted2
20
μV
Equivalent sine power in 50 Ω
87
84
77
dBm
vs. Temperature
88
76
dBm
Input Noise Spectral Density
Inputs shorted
1.5
nV/√Hz
Operating Noise Floor
RSOURCE = 50 Ω/2
78
dBm
Output Resistance
Pin 4 to ground
10
12.5
15
kΩ
Internal Load Capacitance
3.5
pF
Response Time
Small signal, 10% to 90%, 0 mV to 100 mV, CL = 2 pF
400
ns
Large signal, 10% to 90%, 0 V to 2.4 V, CL = 2 pF
500
ns
Upper Usable Frequency
500
MHz
Lower Usable Frequency
AC-coupled input
10
Hz
AMPLIFIER CELL CHARACTERISTICS
Cell Bandwidth
3 dB
900
MHz
Cell Gain
14.3
dB
INPUT CHARACTERISTICS
DC Common-Mode Voltage
AC-coupled input
3.2
V
Common-Mode Range
Either input (small signal)
0.3
+1.6
VS 1
V
DC Input Offset Voltage3
RSOURCE ≤ 50 Ω
50
500
μV
Drift
0.8
μV/°C
Incremental Input Resistance
Differential
1.1
kΩ
Input Capacitance
Either pin to ground
1.4
pF
Bias Current
Either input
10
25
μA
POWER INTERFACES
Supply Voltage
2.7
5.5
V
Supply Current
VENB ≥ 2 V
8
10
mA
Disabled
VENB ≤ 1 V
150
750
μA
1 This can be adjusted downward by adding a shunt resistor from the output to ground. A 50 kΩ resistor reduces the nominal slope to 20 mV/dB.
2 This can be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V.
3 Normally nulled automatically by internal offset correction loop and can be manually nulled by a voltage applied between Pin 3 and ground; see the
Applications Information section.
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