参数资料
| 型号： | AD8326AREZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | IC LINE DVR CATV PROG 28TSSOP |
| 产品变化通告： | AD8326 Series Discontinuation 28/Feb/2012 |
| 标准包装： | 50 |
| 类型： | 线路驱动器，发射器 |
| 应用： | CATV |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-HTSSOP |
| 包装： | 管件 |
REV. 0
AD8326
–12–
Output Bias, Impedance, and Termination
The outputs have a dc bias level of approximately VCC/2, there-
fore they should be ac-coupled before being applied to the load.
The differential output impedance of the AD8326 is internally
maintained at 75
, regardless of whether the amplifier is in
transmit enable mode or transmit disable mode, eliminating the
need for external back termination resistors. A 1:1 transformer
is used to couple the amplifier’s differential output to the coaxial
cable while maintaining a proper impedance match. If the out-
put signal is being evaluated on standard 50
test equipment, a
minimum loss 75
–50 pad must be used to provide the test
circuit with proper impedance match.
Single Supply Operation
The 12 V supply should be delivered to each of the VCC pins via
a low impedance power bus to ensure that each pin is at the
same potential. The power bus should be decoupled to ground using
a 10
F tantalum capacitor located close to the AD8326ARP.
In addition to the 10
F capacitor, each V
CC pin should be
individually decoupled to ground with 0.1
F ceramic chip
capacitors located close to the pins. The pin labeled BYP (Pin
21) should also be decoupled with a 0.1
F capacitor. The PCB
should have a low-impedance ground plane covering all unused
portions of the board, except in the area of the input and output
traces in close proximity to the AD8326 and output transformer. All
ground and VEE pins of the AD8326ARP must be connected to
the ground plane to ensure proper grounding of all internal nodes.
Pin 28 and the exposed pad should be connected to ground.
Dual Supply Operation
The +5 V supply power should be delivered to each of the VCC
pins via a low impedance power bus to ensure that each pin is at
the same potential. The –5 V supply should also be delivered to
each of the VEE pins with a low impedance bus. The power buses
should be decoupled to ground with a 10
F tantalum capacitor
located close to the AD8326ARE. In addition to the 10
F capaci-
tor, all VCC, VEE and BYP pins should be individually decoupled to
ground with 0.1
F ceramic chip capacitors located close to the
pins. The PCB should have a low-impedance ground plane
covering all unused portions of the board, except in the area of
the input and output traces in close proximity to the AD8326
and output transformer. All ground pins of the AD8326ARE must
be connected to the ground plane to ensure proper grounding of
all internal nodes. Pin 28 and the exposed thermal pad should
both be tied to ground.
Signal Integrity Layout Considerations
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
technique is mandatory. The differential input and output traces
should be kept as short as possible. It is also critical to make
sure that all differential signal paths are symmetrical in length
and width. In addition, the input and output traces should be
kept far apart in order to minimize coupling (crosstalk) through
the board. Following these guidelines will improve the overall
performance of the AD8326 in all applications.
Thermal Layout Considerations
As integrated circuits become denser, smaller, and more power-
ful, they often produce more heat. Therefore when designing PC
boards, the layout must be able to draw heat away from the higher
power devices. The AD8326ARE draws up to 1.5 W when running
at +65 dBmV with
±5 V supplies. The AD8326ARP draws a
maximum of 2 W at +67 dBmV with a +12 V supply.
The following guidelines should be used for both the AD8326ARE
and AD8326ARP.
First and foremost, the exposed thermal pad should be soldered
directly to a substantial ground plane that adequately absorbs
heat away from the AD8326 package. This is the simplest, and
most important step in thermally managing the power dissipated in
the AD8326. Increasing the area of copper beneath the AD8326
will lower the thermal resistance in the PCB and more effectively
allow air to remove the heat from the PCB, and consequently,
from the AD8326.
Secondly, thermal stitching is a method for increasing thermal
capacity of the PCB. Additionally, thermal stitching can be used
to provide a thermally efficient area onto which the AD8326
may be soldered. Thermal stitching is accomplished by using a
number of plated through holes (or vias) densely populated in
the solder pad area (but not confined to the size of the TSSOP
or PSOP2 exposed thermal pad). This technique maximizes the
copper area where the package is attached to the PCB increas-
ing the thermal mass or capacity by utilizing more than one
copper plane. This method of thermal management should be
applied in close proximity to the exposed thermal pad.
Another important guideline is to utilize a multilayer PCB with
the AD8326. Lowering the PCB thermal resistance using several
layers will generally increase thermal mass resulting in cooler
junction temperatures.
Using the techniques described above and dedicating 2.9 square
inches of thermally enhanced PCB area, the AD8326 in either
package can operate at safe junction temperatures. Figures 12-17
show the above practices in use on the AD8326ARE-EVAL board.
Initial Power-Up
When the supply is first applied to the AD8326, the gain setting
of the amplifier is indeterminate. Therefore, as power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0), preventing forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the desired
level by following the procedure in the SPI Programming and
Gain Adjustment section. The TXEN pin can then be brought
from Logic 0 to Logic 1, enabling forward signal transmission at
the desired gain level.
Asynchronous Power-Down
The asynchronous TXEN pin is used to place the AD8326 into
“Between Burst” mode while maintaining a differential output
impedance of 75
. Applying Logic 0 to the TXEN pin acti-
vates the on-chip reverse amplifier, providing a 72% reduction
in consumed power. For 12 V operation, the supply current is
typically reduced from 159 mA to 44 mA. In this mode of
operation, between burst noise is minimized and the amplifier
can no longer transmit in the upstream direction. In addition
to the TXEN pin, the AD8326 also incorporates an asynchro-
nous
SLEEP pin, which may be used to further reduce the supply current
to approximately 4 mA. Applying Logic 0 to the
SLEEP pin
places the amplifier into
SLEEP mode. Transitioning into or
out of
SLEEP mode will result in a transient voltage at the
output of the amplifier.
OBSOLETE
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD8326ARP | 制造商:Analog Devices 功能描述:SP AMP LINE DRVR AMP SGL 5.25V/12.6V 28PSOP-II - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:PSOP HIGH OUTPUT POWER CATV LINE DRIVER - Bulk |
| AD8326ARP-EVAL | 制造商:Analog Devices 功能描述:AD8326 PSOP EVALUATION BOARD 制造商:Analog Devices 功能描述:AD8326 PSOP EVALUATION BOARD - Bulk |
| AD8326ARP-REEL | 制造商:Analog Devices 功能描述: |
| AD8326ARPZ | 制造商:Analog Devices 功能描述:SP AMP LINE DRVR AMP SGL 5.25V/12.6V 28PSOP-II - Rail/Tube |
| AD8327 | 制造商:AD 制造商全称:Analog Devices 功能描述:5 V CATV Line Driver Coarse Step Output Power Control |
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