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参数资料
| 型号： | AD8356A-LEG |
| 厂商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分类： | 音频控制 |
| 英文描述： | 2.1-Channel Digital Audio Amplifier with Headphone Driver |
| 中文描述： | 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, LEAD FREE, LQFP-48 |
| 文件页数： | 3/4页 |
| 文件大小： | 326K |
| 代理商： | AD8356A-LEG |
ES MT
AD8356A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.3 3/33
20
SRA
O
Subwoofer-right channel output (+)
21
GNDSR
P
Ground for subwoofer-right channel
22
SRB
O
Subwoofer-right channel output (-)
23
VDDSRB
P
Supply for subwoofer-right channel B
(Note2)
24
set
Re
I
Reset, low active
Schmitt trigger TTL input buffer
25
PD
I
Power down, low active
Schmitt trigger TTL input buffer
26
ERROR
O
ERROR output
Open-drain output
27
SA0
I
I
2
C select address 0
Schmitt trigger TTL input buffer
28
SA1
I
I
2
C select address 1
Schmitt trigger TTL input buffer
29
SCL
I
I
2
C serial clock input
Schmitt trigger TTL input buffer
30
SDA
I
I
2
C serial data input
Schmitt trigger TTL input buffer with
open-drain output
31
DEF
I
Default volume, 0=Mute, 1=Un-Mute
Schmitt trigger TTL input buffer
32
PWMSA
O
Half-bridge, sub-woofer channel output
TTL output buffer
33
AVDD
P
Analog supply
(Note1)
34
AGND
P
Analog ground
35
HPR
O
Headphone right channel output
36
HPL
O
Headphone left channel output
37
HP-SPK
I
Headphone detection
38
VDDRB
P
Supply for right channel B
(Note2)
39
RB
O
Right channel output (-)
40
GNDR
P
Ground for Right channel
41
RA
O
Right channel output (+)
42
VDDRA
P
Supply for right channel A
(Note2)
43
VDDLA
P
Supply for left channel A
(Note2)
44
LA
O
Left channel output (+)
45
GNDL
P
Ground for left channel
46
LB
O
Left channel output (-)
47
VDDLB
P
Supply for left channel B
(Note2)
48
PLL_Byp
I
PLL Bypass
Schmitt trigger TTL input buffer
Note1
：
These pins provide the supply for digital PWM controller, headphone drivers, built-in PLL and
protection circuits except for loudspeaker short-circuit protection circuits.
Note2
：
These pins provide the supply for loudspeaker driver stages, which are known as “PVDD”.
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