参数资料
| 型号： | AD8557ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/24页 |
| 文件大小： | 0K |
| 描述： | IC AMP CHOPPER 2MHZ 55MA 8SOIC |
| 标准包装： | 98 |
| 系列： | DigiTrim® |
| 放大器类型： | 断路器（零漂移） |
| 电路数： | 1 |
| 增益带宽积： | 2MHz |
| 电流 - 输入偏压： | 18nA |
| 电压 - 输入偏移： | 2µV |
| 电流 - 电源： | 1.8mA |
| 电流 - 输出 / 通道： | 55mA |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 管件 |
| 产品目录页面： | 771 (CN2011-ZH PDF) |
AD8557
Rev. C | Page 17 of 24
Table 10. Timing Specifications
Timing Parameter
Description
Specification
tw0
Pulse width for loading 0 into shift register
Between 50 ns and 10 s
tw1
Pulse width for loading 1 into shift register
≥50 s
tws
Width between pulses
≥10 s
Table 11. 38-Bit Serial Word Format
Field No.
Bits
Description
0
0 to 11
12-bit start of packet 1000 0000 0001
1
12 to 13
2-bit function
00: change sense current
01: simulate parameter value
10: program parameter value
11: read parameter value
2
14 to 15
2-bit parameter
00: second stage gain code
01: first stage gain code
10: output offset code
11: other functions
3
16 to 17
2-bit dummy 10
4
18 to 25
8-bit value
Parameter 00 (second stage gain code): 3 LSBs used
Parameter 01 (first stage gain code): 7 LSBs used
Parameter 10 (output offset code): all 8 bits used
Parameter 11 (other functions)
Bit 0 (LSB): master fuse
Bit 1: fuse for production test at Analog Devices
5
26 to 37
12-bit end of packet 0111 1111 1110
A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 s, the 38-bit serial word transfers
in 2.3 ms. Table 11 summarizes the word format.
Field 0 and Field 5 are the start-of-packet field and end-of-
packet field, respectively. Matching the start-of-packet field with
1000 0000 0001 and the end-of-packet field with 0111 1111
1110 ensures that the serial word is valid and enables decoding
of the other fields.
Field 3 breaks up the data and ensures that no data combination
can inadvertently trigger the start-of-packet and end-of-packet
fields. Field 0 should be written first and Field 5 written last.
Within each field, the MSB must be written first and the LSB
written last. The shift register features power-on reset to mini-
mize the risk of inadvertent programming; power-on reset
occurs when VDD is between 0.7 V and 2.2 V.
Initial State
Initially, all the polysilicon fuses are intact. Each parameter has
the value 0 assigned (see Table 12).
Table 12. Initial State Before Programming
Second Stage Gain Code = 0
Second Stage Gain = 10
First stage gain code = 0
First stage gain = 2.8
Output offset code = 0
Output offset = VSS
Master fuse = 0
Master fuse not blown
When power is applied to a device, parameter values are taken
either from internal registers, if the master fuse is not blown,
or from the polysilicon fuses, if the master fuse is blown.
Programmed values have no effect until the master fuse is
blown. The internal registers feature power-on reset, so the
unprogrammed devices enter a known state after power-up.
Power-on reset occurs when VDD is between 0.7 V and 2.2 V.
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