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| 型号： | AD8561AR |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC COMPARATOR SNGL 7NS 8-SOIC |
| 标准包装： | 98 |
| 类型： | 通用 |
| 元件数： | 1 |
| 输出类型： | CMOS，补充型，TTL |
| 电压 - 电源，单路/双路(±)： | 3 V ~ 10 V，±1.5 V ~ 5 V |
| 电压 - 输入偏移（最小值）： | 7mV @ 5V |
| 电流 - 输入偏压（最小值）： | 6µA @ 5V |
| 电流 - 静态（最大值）： | 6mA，3.3mA，5.5mA |
| CMRR, PSRR（标准）： | 85dB CMRR，65dB PSRR |
| 传输延迟（最大）： | 9.8ns |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 安装类型： | 表面贴装 |
| 包装： | 管件 |
AD8561
–7–
APPLICATIONS
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator or amplifier, proper design
and layout techniques should be used to ensure optimal perfor-
mance from the AD8561. The performance limits of high speed
circuitry can easily be a result of stray capacitance, improper
ground impedance or other layout issues.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
AD8561. Source resistance in combination with equivalent
input capacitance could cause a lagged response at the input,
thus delaying the output. The input capacitance of the AD8561
in combination with stray capacitance from an input pin to
ground could result in several picofarads of equivalent capaci-
tance. A combination of 3 k
Ω source resistance and 5 pF of
input capacitance yields a time constant of 15 ns, which is
slower than the 5 ns capability of the AD8561. Source imped-
ances should be less than 1 k
Ω for the best performance.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1
μF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin, Pin 1 and Pin 4, to ground. These capacitors will
reduce any potential voltage ripples from the power supply. In
addition, a 10 nF ceramic capacitor should be placed as close as
possible from the power supply pins to ground. These capacitors
act as a charge reservoir for the device during high frequency
switching.
A ground plane is recommended for proper high speed perfor-
mance. This can be created by using a continuous conductive
plane over the surface of the circuit board, only allowing breaks
in the plane for necessary current paths. The ground plane
provides a low inductive ground, eliminating any potential dif-
ferences at different ground points throughout the circuit board
caused from “ground bounce.” A proper ground plane also
minimizes the effects of stray capacitance on the circuit board.
REPLACING THE LT1016
The AD8561 is pin compatible with the LT1016 comparator.
While it is easy to replace the LT1016 with the higher perfor-
mance AD8561, please note that there are differences, and it is
useful to check these to ensure proper operation.
There are five major differences between the AD8561 and the
LT1016—input voltage range, input bias currents, speed, out-
put swing and power consumption.
When operated on a +5 V single supply, the LT1016 has an
input voltage range from +1.25 V to +3.5 V. The AD8561 has a
wider input range from 0 V to 3.0 V. Signals above 3.0 V may
result in slower response times (see Figure 8). If both signals
exceed 3.0 V, the signals may be shifted or attenuated to bring
them into range, keeping in mind the note about source resis-
tance in Optimizing High Speed Performance. If only one of the
signals exceeds 3.0 V only slightly, and the other signal is always
well within the 0 V to 3 V range, the comparator may operate
without changes to the circuit.
Example: A comparator compares a fast moving signal to a
fixed 2.5 V reference. Since the comparator only needs to oper-
ate when the signal is near 2.5 V, both signals will be within the
input range (near 2.5 V and well under 3.0 V) when the com-
parator needs to change output.
Note that signals much greater than 3.0 V will result increased
input currents and may cause the device to operate more slowly.
The input bias current of the AD8561 is lower (–3
μA typical)
than the LT1016 (+5
μA typical), and the current flows out of
the AD8561 and into LT1016. If relatively low value resistors
and/or low impedance sources are used on the inputs, the volt-
age shift due to bias current should be small.
The AD8561 (6.75 ns typical) is faster than the LT1016 (10 ns
typical). While this is beneficial to many systems, timing may
need to be adjusted to take advantage of the higher speed.
The AD8561 has slightly more output voltage swing, from 0.2 V
above ground to within 1.1 V of the positive supply voltage.
The AD8561 uses less current (typically 5 mA) than the LT1016
(typically 25 mA).
INCREASING OUTPUT SWING
Although not required for normal operation, the output voltage
swing of the AD8561 can be increased by connecting a 5 k
Ω
resistor from the output of the device to the V+ power supply.
This configuration can be useful in low voltage power supply
applications where maximizing output voltage swing is impor-
tant. Adding a 5 k
Ω pull-up resistor to the device’s output will
not adversely affect the specifications of the AD8561.
OUTPUT LOADING CONSIDERATIONS
The AD8561 output can deliver up to 40 mA of output current
without any significant increase in propagation delay. The
output of the device should not be connected to more than
twenty (20) TTL input logic gates, or drive a load resistance
less than 100
Ω.
To ensure the best performance from the AD8561 it is impor-
tant to minimize capacitive loading of the output of the device.
Capacitive loads greater than 50 pF will cause ringing on the
output waveform and will reduce the operating bandwidth of
the comparator.
SETUP AND HOLD TIMES FOR LATCHING THE
OUTPUT
The latch input, Pin 5, can be used to retain data at the output
of the AD8561. When the voltage at the latch input goes high,
the output of the device will remain constant regardless of the
input voltages. The setup time for the latch is 2 ns–3 ns and the
hold time is 3 ns. This means that to ensure data retention at
the output, the input signal must be valid at least 5 ns before
the latch pin goes high and must remain valid at least 3 ns after
the latch pin goes high. Once the latch input voltage goes low,
new output data will appear in approximately 8 ns.
A logic high for the latch input is a minimum of +2.0 V and a
logic low is a maximum of +0.8 V. This makes the latch input
easily interface with TTL or CMOS logic gates. The latch
circuitry in the AD8561 has no built-in hysteresis.
Rev. B
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|---|---|
| AD8561AR-REEL | 功能描述:IC COMP 7NS ULTRA-FAST 8-SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| AD8561AR-REEL7 | 功能描述:IC COMP 7NS ULTRA-FAST 8-SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| AD8561ARU | 制造商:Analog Devices 功能描述: |
| AD8561ARUREEL | 制造商:AD 功能描述:New |
| AD8561ARU-REEL | 功能描述:IC COMP 7NS ULTRA-FAST 8-TSSOP RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
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