AD871
REV. A
–10–
Figure 12 shows the common-mode rejection performance vs.
frequency for a 1 V p-p common-mode input. This excellent
common-mode rejection over a wide bandwidth affords the user
the opportunity to eliminate many potential sources of input
noise as common mode by using the differential input structure
of the AD871.
C
–40
–70
–100
–90
–80
–60
–50
INPUT FREQUENCY – Hz
10k
100k
10M
1M
Figure 12. Common-Mode Rejection vs. Input Frequency,
1 V p-p Input
Figures 13 and 14 illustrate typical input connections for single
ended inputs.
1
2
V
INA
V
INB
AD871
6
1V
Figure 13. AD871 Single-Ended Input Connection
1
2
V
INA
V
INB
AD871
R
T
6
1V
Figure 14. AD871 Single-Ended Input Connection Using a
Shielded Cable
The cable shield is used as the ground connection for the V
INB
input, providing the best possible rejection of the cable noise
from the input signal. Note also that the high input impedance
of the AD871 allows the user to select the termination imped-
ance, be it 50 ohms, 75 ohms, or some other value. Further-
more, unlike many flash converters, most AD871 applications
will not require an external buffer amplifier. If such an amplifier
is required, we suggest either the AD811 or AD9617.
Figure 15 illustrates how external amplifiers may be used to
convert a single-ended input into a differential signal. The resis-
tor values of 536
and 562
were selected to provide opti-
mum phase matching between U1 and U2.
V
INA
V
INB
AD871
U2
U1
V
IN
(
6
0.5V)
562
V
536
V
562
V
536
V
Figure 15. Single-Ended to Differential Connections;
U1, U2 = AD811 or AD9617
The use of the differential input signal can help to minimize
even-order distortion from the input THA where performance
beyond –70 dB is desired.
Figure 16 shows the AD871 large signal (–0.5 dB) and small
signal (–20 dB) frequency response.
F
10
–30
10
4
10
8
0
–20
10
5
–10
10
6
10
7
INPUT FREQUENCY – Hz
Figure 16. Full Power (–0.5 dB) and Small Signal
Response (–20 dB) vs. Input Frequency
The AD871’s wide input bandwidth facilitates rapid acquisition
of transient input signals: the input THA can typically settle to
12-bit accuracy from a full-scale input step in less than 80 ns. Fig-
ure 17 illustrates the typical acquisition of a full-scale input step.
4400
0
100
1200
400
800
0
2400
1600
2000
2800
3200
3600
4000
80
60
40
20
M
TIME – ns
Figure 17. Typical AD871 Settling Time