参数资料
型号: AD8801
厂商: Analog Devices, Inc.
英文描述: Octal 8-Bit TrimDAC with Power Shutdown(带电源关断的八路8位微调D/A转换器)
中文描述: 八进制8位功耗关断TrimDAC(带电源关断的八路8位微调的D / A转换器)
文件页数: 5/16页
文件大小: 223K
代理商: AD8801
AD8801/AD8803
REV. A
–5–
For example, when V
REFH
= +5 V and V
REFL
= 0 V the follow-
ing output voltages will be generated for the following codes:
D
V
OX
Output State
(V
RE FH
= +5 V, V
RE FL
= 0 V)
255
128
1
0
4.98 V
2.50 V
0.02 V
0.00 V
Full-Scale
Half-Scale (Midscale Reset Value)
1 LSB
Zero-Scale
RE FE RE NCE INPUT S (V
RE FH
, V
RE FL
)
T he reference input pins set the output voltage range of all eight
DACs. In the case of the AD8801 only the V
REFH
pin is avail-
able to establish a user designed full-scale output voltage. T he
external reference voltage can be any value between 0 and V
DD
but must not exceed the V
DD
supply voltage. In the case of the
AD8803, which has access to the V
REFL
which establishes the
zero-scale output voltage, any voltage can be applied between
0 V and V
DD
. V
REFL
can be smaller or larger in voltage than
V
REFH
since the DAC design uses fully bidirectional switches as
shown in Figure 3. T he input resistance to the DAC has a code
dependent variation that has a nominal worst case measured at
55
H
, which is approximately 2 k
. When V
REFH
is greater than
V
REFL
, the REFL reference must be able to sink current out of
the DAC ladder, while the REFH reference is sourcing current
into the DAC ladder. T he DAC design minimizes reference
glitch current maintaining minimum interference between DAC
channels during code changes.
DAC OUT PUT S (O1–O8)
T he eight DAC outputs present a constant output resistance of
approximately 5 k
independent of code setting. T he distribu-
tion of R
OUT
from DAC to DAC typically matches within
±
1%.
However, device to device matching is process lot dependent
having a
±
20% variation. T he change in R
OUT
with temperature
has a 500 ppm/
°
C temperature coefficient. During power shut-
down all eight outputs are open circuited.
DAC
REG
#1
EN
ADDR
DEC
DAC
REG
#8
D10
D9
D8
D7
SER
REG
D
D0
. .
. .
D1
AD8801/AD8803
D7
D0
D8
D7
D0
8
R
R
V
DD
V
REFH
O1
O2
O3
O4
O5
O6
O7
O8
CS
CLK
SDI
SHDN
GND
RS
V
REFL
.
.
(AD8801 ONLY)
(AD8803 ONLY)
Figure 4. Block Diagram
DIGIT AL INT E RFACING
T he AD8801/AD8803 contains a standard three-wire serial in-
put control interface. T he three inputs are clock (CLK ),
CS
and
serial data input (SDI). T he positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 4 block diagram shows more detail of the internal digital cir-
cuitry. When
CS
is taken active low, the clock can load data into
the serial register on each positive clock edge, see T able II.
T able II. Input Logic Control T ruth T able
CS
CLK
Register Activity
1
0
X
P
No effect.
Shifts Serial Register one bit loading the
next bit in from the SDI pin.
Data is transferred from the serial register
to the decoded DAC register. See Figure 5.
P
X
NOT E: P = positive edge, X = don’t care.
T he data setup and data hold times in the specification table
determine the data valid time requirements. T he last 11 bits of
the data word entered into the serial register are held when
CS
returns high. At the same time
CS
goes high it gates the address
decoder which enables one of the eight positive edge triggered
DAC registers, see Figure 5 detail.
DAC 1
DAC 2
DAC 8
ADDR
DECODE
SERIAL
REGISTER
CS
CLK
SDI
Figure 5. Equivalent Control Logic
T he target DAC register is loaded with the last eight bits of the se-
rial data word completing one DAC update. Eight separate 11-bit
data words must be clocked in to change all eight output settings.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 6. T his applies to
digital input pins
CS
, SDI,
RS
,
SHDN
, CLK .
LOGIC
100
Figure 6. Equivalent ESD Protection Circuit
Digital inputs can be driven by voltages exceeding the AD8801/
AD8803 V
DD
value. T his allows 5 V logic to interface directly to
the part when it is operated at 3 V.
相关PDF资料
PDF描述
AD8803 Octal 8-Bit TrimDAC with Power Shutdown(带电源关断八路8位微调D/A转换器)
AD8803AR Octal 8-Bit TrimDAC with Power Shutdown
AD8803AN Octal 8-Bit TrimDAC with Power Shutdown
AD8801AN Octal 8-Bit TrimDAC with Power Shutdown
AD8801AR Octal 8-Bit TrimDAC with Power Shutdown
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