
AD8801/AD8803
REV. A
–3–
ORDERING GUIDE
Package
Model
FTN
Temperature
Description
Option
AD8801AN
RS
–40
°C to +85°C PDIP-16
N-16
AD8801AR
RS
–40
°C to +85°C SO-16
R-16A
AD8803AN
REFL
–40
°C to +85°C PDIP-16
N-16
AD8803AR
REFL
–40
°C to +85°C SO-16
R-16A
AD8803 PIN DESCRIPTIONS
Pin Name
Description
1VREFH
Common High-Side DAC Reference Input
2
O1
DAC Output #1, Addr = 0002
3
O2
DAC Output #2, Addr = 0012
4
O3
DAC Output #3, Addr = 0102
5
O4
DAC Output #4, Addr = 0112
6
SHDN
Reference inputs open circuit, active low, all
DAC outputs open circuit. DAC latch settings
maintained.
7
CS
Chip Select Input, active low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded into the tar-
get DAC register.
8
GND
Ground
9VREFL
Common Low-Side DAC Reference Input
10
CLK
Serial Clock Input, Positive Edge Triggered
11
SDI
Serial Data Input
12
O5
DAC Output #5, Addr = 1002
13
O6
DAC Output #6, Addr = 1012
14
O7
DAC Output #7, Addr = 1102
15
O8
DAC Output #8, Addr = 1112
16
VDD
Positive power supply, specified for operation at
both +3 V and +5 V.
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +8 V
VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, VDD
Operating Temperature Range . . . . . . . . . . . . . –40
°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300
°C
Package Power Dissipation . . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Resistance
θ
JA,
SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
°C/W
P-DIP (N-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
°C/W
AD8801 PIN DESCRIPTIONS
Pin Name
Description
1VREFH
Common DAC Reference Input
2
O1
DAC Output #1, Addr = 0002
3
O2
DAC Output #2, Addr = 0012
4
O3
DAC Output #3, Addr = 0102
5
O4
DAC Output #4, Addr = 0112
6
SHDN
Reference input open circuit, active low, all
DAC outputs open circuit. DAC latch settings
maintained.
7
CS
Chip Select Input, active low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded into the tar-
get DAC register.
8
GND
Ground
9
CLK
Serial Clock Input, Positive Edge Triggered
10
SDI
Serial Data Input
11
O5
DAC Output #5, Addr = 1002
12
O6
DAC Output #6, Addr = 1012
13
O7
DAC Output #7, Addr = 1102
14
O8
DAC Output #8, Addr = 1112
15
RS
Asynchronous preset to midscale output setting,
active low. Loads all DAC latches with 80H.
16
VDD
Positive power supply, specified for operation at
both +3 V and +5 V.
PIN CONFIGURATIONS
VREFH
O1
VDD
RS
O4
SHDN
CS
O6
O5
SDI
O2
O3
O8
O7
GND
CLK
1
2
16
15
5
6
7
12
11
10
3
4
14
13
89
TOP VIEW
(Not to Scale)
AD8801
VREFH
O1
VDD
O8
O4
SHDN
CS
O5
SDI
CLK
O2
O3
O7
O6
GND
VREFL
1
2
16
15
5
6
7
12
11
10
3
4
14
13
89
TOP VIEW
(Not to Scale)
AD8803
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.