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参数资料
| 型号： | AD8804 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 12 Channel, 8-Bit TrimDACs with Power Shutdown(12通道,带电源关断8位D/A转换器) |
| 中文描述： | 12通道，8位与电源关断TrimDACs（12通道，带电源关断8位的D / A转换器） |
| 文件页数： | 7/16页 |
| 文件大小： | 379K |
| 代理商： | AD8804 |
AD8802/AD8804
REV. 0
–7–
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage range is determined by the external refer-
ence connected to V
REFH
and V
REFL
pins. See Figure 16 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8802 its V
REFL
is internally connected to GND and
therefore cannot be offset. V
REFH
can be tied to V
DD
and V
REFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation which determines the programmed output
voltage is:
VO
(
Dx
) = (
Dx
)/256
×
(
V
REFH
–
V
REFL
) +
V
REFL
where
Dx
is the data contained in the 8-bit DACx register.
Eq. 1
MSB
O
X
2R
R
P CH
N CH
TO OTHER DACS
R
2R
2R
2R
GND
V
REFL
LSB
DAC
REGISTER
D6
D0
D7
V
REFH
..
.
Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit
For example, when V
REFH
= +5 V and V
REFL
= 0 V, the follow-
ing output voltages will be generated for the following codes:
Output State
(V
REFH
= +5 V, V
REFL
= 0 V)
D
VOx
255
128
1
0
4.98 V
2.50 V
0.02 V
0.00 V
Full Scale
Half Scale (Midscale Reset Value)
1 LSB
Zero Scale
REFERENCE INPUTS (V
REFH
, V
REFL
)
The reference input pins set the output voltage range of all
twelve DACs. In the case of the AD8802 only the V
REFH
pin is
available to establish a user designed full-scale output voltage.
The external reference voltage can be any value between 0 and
V
DD
but must not exceed the V
DD
supply voltage. The AD8804
has access to the V
REFL
which establishes the zero-scale output
voltage, any voltage can be applied between 0 V and V
DD
. V
REFL
can be smaller or larger in voltage than V
REFH
since the DAC
design uses fully bidirectional switches as shown in Figure 16.
The input resistance to the DAC has a code dependent variation
which has a nominal worst case measured at 55
H
, which is ap-
proximately 1.2 k
. When V
REFH
is greater than V
REFL
, the
REFL reference must be able to sink current out of the DAC
ladder, while the REFH reference is sourcing current into the
DAC ladder. The DAC design minimizes reference glitch cur-
rent maintaining minimum interference between DAC channels
during code changes.
DAC OUTPUTS (O1–O12)
The twelve DAC outputs present a constant output resistance of
approximately 5 k
independent of code setting. The distribu-
tion of R
OUT
from DAC-to-DAC typically matches within
±
1%.
However device-to-device matching is process lot dependent
having a
±
20% variation. The change in R
OUT
with temperature
has a 500 ppm/
°
C temperature coefficient. During power shut-
down all twelve outputs are open-circuited.
CS
CLK
SDI
SHDN
AD8802/AD8804
D7
D0
ADDR
DEC
EN
D11
D10
D9
D8
D7
SER
REG
D
D0
DAC
REG
#1
R
V
DD
V
REFH
D7
D0
DAC
12
DAC
REG
#12
R
D1
8
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
GND
RS
(AD8802 ONLY)
V
(AD8804 ONLY)
Figure 17. Block Diagram
DIGITAL INTERFACING
The AD8802/AD8804 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK),
CS
and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 17 block diagram shows more detail of the internal digital
circuitry. When
CS
is taken active low, the clock can load data
into the serial register on each positive clock edge, see Table II.
Table II. Input Logic Control Truth Table
CS
CLK
Register Activity
1
0
X
P
No effect.
Shifts Serial Register One bit loading the next bit
in from the SDI pin.
Clock should be high when the
CS
returns to the
inactive state.
P
1
P = Positive Edge, X = Don’t Care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 12 bits of
the data word entered into the serial register are held when
CS
returns high. At the same time
CS
goes high it gates the address
decoder which enables one of the twelve positive-edge triggered
DAC registers, see Figure 18 detail.
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| AD8842AN | Precision, Quad, SPST Analog Switches |
| AD8842AR | 8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDAC |
| AD8883B | 60 MHz, 2000 V/us Monolithic Op Amp |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD8804AN | 制造商:Analog Devices 功能描述:DAC 12-CH R-2R 8-bit 20-Pin PDIP N Tube 制造商:Rochester Electronics LLC 功能描述:12CH 8BIT TDAC W/VREFL SHDWN - Bulk |
| AD8804ANZ | 功能描述:IC DAC 8BIT 12CH W/SD 20DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TrimDAC® 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD8804AR | 功能描述:IC DAC 8BIT 12CH W/SD 20-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TrimDAC® 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| AD8804AR-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD8804ARU | 制造商:Analog Devices 功能描述:DAC 12-CH R-2R 8-bit 20-Pin TSSOP |
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