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参数资料
| 型号： | AD8842AR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | 8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDAC |
| 中文描述： | OCTAL, SERIAL INPUT LOADING, 5.4 us SETTLING TIME, 8-BIT DAC, PDSO24 |
| 封装： | 0.300 INCH, SOIC-24 |
| 文件页数： | 2/12页 |
| 文件大小： | 506K |
| 代理商： | AD8842AR |
AD8842–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H
Resolution
N
Integral Nonlinearity Error
INL
Differential Nonlinearity
DNL
Full-Scale Gain Error
G
FSE
Output Offset
V
BZE
Output Offset Drift
TCV
BZ
8
Bits
LSB
LSB
LSB
mV
μ
V/
°
C
±
0.2
±
0.4
2
5
5
±
1
±
1
All Devices Monotonic
PR
= 0, Sets D = 80
H
PR
= 0, Sets D = 80
H
25
VOLTAGE INPUTS—Applies to All Inputs V
IN
x
Input Voltage Range
1
Input Resistance
Input Capacitance
IVR
R
IN
C
IN
±
3
12
±
4
19
9
V
k
pF
DAC OUTPUTS—Applies to All Outputs V
OUT
x
Voltage Range
1
Output Current
Capacitive Load
OVR
I
OUT
C
L
R
L
= 10 k
V
OUT
< 1.5 LSB
No Oscillation
±
3
±
3
±
4
V
mA
pF
500
DYNAMIC PERFORMANCE—Applies to All DACs
Full Power Gain Bandwidth
1
Slew Rate
Positive
Negative
Total Harmonic Distortion
GBW
V
IN
x =
±
3 V
P
, R
L
= 2 k
, C
L
= 10 pF
Measured 10% to 90%
V
OUT
x = +5.5 V
V
OUT
x = –5.5 V
V
IN
x = 4 V p-p, D = FF
H
, f = 1 kHz,
f
LPF
= 80 kHz, R
L
= 1 k
f = 1kHz, V
IN
= 0 V
±
1 LSB Error Band, D = 00
H
to FF
H
D = FF
H
to 00
H
Measured Between Adjacent
Channels, f = 100 kHz
V
IN
x = 0 V, D = 0 to 255
10
10
50
kHz
SR+
SR–
THD
0.5
1.0
1.0
1.8
0.01
V/
μ
s
V/
μ
s
%
Spot Noise Voltage
Output Settling Time
e
N
t
S
78
2.9
5.4
nV/
√
Hz
μ
s
μ
s
Channel-to-Channel Crosstalk
C
T
72
5
dB
nV-s
Digital Feedthrough
Q
POWER SUPPLIES
Positive Supply Current
Negative Supply Current
Power Dissipation
2
Power Supply Rejection
Power Supply Range
I
DD
I
SS
P
DISS
PSRR
PSR
PR
= 0 V
PR
= 0 V
10
9
95
0.0001
5.00
14
13
135
0.01
5.25
mA
mA
mW
%/%
V
PR
= 0 V,
V
DD
=
±
5%
V
DD
, |V
SS
|
4.75
DIGITAL INPUTS
Logic High
Logic Low
Input Current
Input Capacitance
Input Coding
V
IH
V
IL
I
L
C
IL
2.4
V
V
μ
A
pF
0.8
±
10
7
Offset Binary
DIGITAL OUTPUT
Logic High
Logic Low
V
OH
V
OL
I
OH
= –0.4 mA
I
OL
= 1.6 mA
3.5
V
V
0.4
TIMING SPECIFICATIONS
1
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
Load Edge to Next Clock Edge
t
CH
, t
CL
t
DS
t
DH
t
PD
t
LD
t
PR
t
CKLD
t
LDCK
60
40
20
ns
ns
ns
ns
ns
ns
ns
ns
80
70
50
30
60
NOTES
1
Guaranteed by design, not subject to production test.
2
Calculated
limit = 5 V
×
(I
DD
+ I
SS
).
Specifications subject to change without notice.
REV. 0
–2–
(V
DD
= +5 V, V
SS
= –5 V, All V
IN
x = +3 V, T
A
= –40
°
C to +85
°
C, unless otherwise noted.)
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