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参数资料
| 型号： | AD9050BRS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 10-Bit, 40 MSPS/60 MSPS A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | SSOP-28 |
| 文件页数： | 9/12页 |
| 文件大小： | 151K |
| 代理商： | AD9050BRS |
AD9050
–9–
REV. B
Overdrive of the Analog Input
Special care was taken in the design of the analog input section
of the AD9050 to prevent damage and corruption of data when
the input is overdriven. T he nominal input range is +2.788 V to
3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range com-
parators detect when the analog input signal is out of this range
and shut the T /H off. T he digital outputs are locked at their
maximum or minimum value (i.e., all “0” or all “1”). T his pre-
cludes the digital outputs from changing to an invalid value
when the analog input is out of range.
When the analog input signal returns to the nominal range, the
out-of-range comparators switch the T /H back to the active
mode and the device recovers in approximately 10 ns.
T he input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +6.0 V to –1.0 V.
T iming
T he performance of the AD9050 is very insensitive to the duty
cycle of the clock. Pulse width variations of as much as
±
10%
will cause no degradation in performance. (see Figure 13, SNR
vs. Clock Pulse Width).
T he AD9050 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (t
PD
)
after the rising edge of the encode command (refer to the
AD9050 T iming Diagram). T he length of the output data lines
and loads placed on them should be minimized to reduce tran-
sients within the AD9050; these transients can detract from the
converter’s dynamic performance.
T he minimum guaranteed conversion rate of the AD9050 is
3 MSPS. Below a nominal of 1.5 MSPS the internal T /H
switches to a track function only. T his precludes the T /H from
drooping to the rail during the conversion process and mini-
mizes saturation issues. At clock rates below 3 MSPS dynamic
performance degrades. T he AD9050 will operate in burst mode
operation, but the user must flush the internal pipeline each
time the clock stops. T his requires five clock pulses each time
the clock is restarted for the first valid data output (refer to Fig-
ure 2 T iming Diagram).
Power Dissipation
T he power dissipation specification in the parameter table is
measured under the following conditions: encode is 40 MSPS
or 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, the digi-
tal outputs are loaded with approximately 7 pF (10 pF maxi-
mum) and V
DD
is 5 V. T hese conditions intend to reflect actual
usage of the device.
As shown in Figure 4, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. Also the
loading determines the power dissipated in the output stages.
From an ac standpoint, the capacitive loading will be the key
(refer to Equivalent Output Stage).
T he analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. T his minimizes power in the
output stages, but is not realistic from a usage standpoint.
T he dissipation in the output stages can be minimized by inter-
facing the outputs to 3 V logic (refer to USING T HE AD9050,
3 V System). T he lower output swings minimize consumption.
Refer to Figure 4 for performance characteristics.
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9050 (Pin 3, V
REF
Output). In normal operation the internal
reference is used by strapping Pins 3 and 4 of the AD9050 to-
gether. T he internal reference has 500
μ
A of extra drive current
that can be used for other circuits.
Some applications may require greater accuracy, improved tem-
perature performance, or adjustment of the gain of the AD9050,
which cannot be obtained by using the internal reference. For
these applications, an external +2.5 V reference can be used to
connect to Pin 4 of the AD9050. T he VREF
IN
requires 5
μ
A of
drive current.
T he input range can be adjusted by varying the reference volt-
age applied to the AD9050. No appreciable degradation in per-
formance occurs when the reference is adjusted
±
5%. T he
full-scale range of the ADC tracks reference voltage changes
linearly.
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| AD9051 | 10-Bit, 60 MSPS A/D Converter |
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| AD9051BRS | 10-Bit, 60 MSPS A/D Converter |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9050BRS-60 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 60Msps 10-bit Parallel 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:10BIT 40MSPS ADC - Bulk |
| AD9050JR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 10-Bit |
| AD9050JRS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 10-Bit |
| AD9051 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 60 MSPS A/D Converter |
| AD9051/PCB | 制造商:Analog Devices 功能描述:10-BIT 60 MSPS ADC - Bulk |
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