参数资料
| 型号： | AD9051BRSRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/11页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 60MSPS 28-SSOP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,500 |
| 位数： | 10 |
| 采样率（每秒）： | 60M |
| 数据接口： | 并联 |
| 转换器数目： | 3 |
| 功率耗散（最大）： | 315mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
REV.
AD9051
–9–
THEORY OF OPERATION
Refer to the block diagram on the front page.
The AD9051 employs a subranging architecture with digital
error correction. This combination of design techniques ensures
true 10-bit accuracy at the digital outputs of the converter.
At the input, the analog signal is buffered by a high speed
differential buffer and applied to a track-and-hold (T/H) that
holds the analog value present when the unit is strobed with
an ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.
Error correction and decode logic correct and align data from
the two conversions and present the result as a 10-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in
five pipeline delays for the output data. Refer to the AD9051
Timing Diagram.
USING THE AD9051
3 V System
The digital input and outputs of the AD9051 can be easily
configured to directly interface to 3 V logic systems. The encode
input (Pin 13) is TTL compatible with a logic threshold of
1.5 V. This input is actually a CMOS stage (refer to Equivalent
Encode Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to 5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
The AD9051 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer
to AD9051 Output Stage) with isolated supply pins (Pins 20,
22 VDD). By varying the voltage on the VDD pins, the digital
output levels vary respectively. By connecting Pins 20 and 22 to
the 3 V logic supply, the AD9051 will supply 3 V output
levels. Care should be taken to filter and isolate the output
supply of the AD9051 as noise could be coupled into the
ADC, limiting performance.
Analog Input
The analog input of the AD9051 is a differential input buffer
(refer to AD9051 Equivalent Analog Input). The differential
inputs are internally biased at 2.5 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-endedly or differentially (for
best dynamic performance, impedances at AIN and AINB
should match).
Figure 3 shows typical connections for the analog inputs when
using the AD9051 in a dc-coupled system with single-ended
signals. All components are powered from a single 5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9051.
AC coupling of the analog inputs of the AD9051 is easily
accomplished. Figure 4 shows capacitive coupling of a single-
ended signal while Figure 5 shows transformer coupling
differentially into the AD9051.
VIN
–0.625V
TO
+0.625V
5V
AD9631
140
5V
AD9051
9
10
5V
1k
AD820
1k
0.1 F
Figure 3. Single Supply, Single-Ended, DC-Coupled
AD9051
+5V
AD9631
140
5V
AD9051
9
10
–5V
0.1 F
VIN
–0.625V
TO
+0.625V
Figure 4. Single-Ended, Capacitively-Coupled AD9051
+5V
5V
9
10
–5V
0.1 F
AD9051
T1-1T
50
VIN
–0.625V
TO
+0.625V
AD9631
140
Figure 5. Differentially Driven AD9051 Using Trans-
former Coupling
The AD830 provides a unique method of providing dc level
shift for the analog input. Using the AD830 allows a great deal
of flexibility for adjusting offset and gain. Figure 6 shows the
AD830 configured to drive the AD9051. The offset is provided
by the internal biasing of the AD9051 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
1
2
3
4
AD830
+15V
–5V
7
10
9
0.1 F
+5V
AD9051
VIN
–0.625V
TO
+0.625V
Figure 6. Level-Shifting with the AD830
C
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| AD9051BRSRL-2V | 功能描述:IC ADC 10BIT 60MSPS 28-SSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
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