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参数资料
| 型号： | AD9054 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit, 200 MSPS A/D Converter |
| 中文描述： | 8位，200 MSPS的A / D转换 |
| 文件页数： | 14/20页 |
| 文件大小： | 303K |
| 代理商： | AD9054 |
AD9054
–14–
REV. 0
E VALUAT ION BOARD
T he AD9054 evaluation board offers an easy way to test the
AD9054. It provides dc biasing for the analog input, generates
the latch clocks for both full speed and demuxed modes, and in-
cludes a reconstruction DAC. T he board has several different
modes of operation, and is shipped in the following configuration:
DC-Coupled Analog Input
Demuxed Outputs
Differential Clocks
Internal Voltage Reference.
VREF OUT
VREF IN
AIN
AIN
DEMUX
AD9054
DS
DS
ENC
ENC
A PORT
'574
A PORT
'574
DAC
CLK A
CLK B
CLOCKING
ENC
ENC
S102
VREF EXT
S103
DC BIAS
50
V
AIN
5V
D FF
D
C
RESET
BUTTON
CLK A
CLK B
S104
S105
ENC
50
V
ENC
50
V
Figure 37. PCB Block Diagram
Analog Input
T he evaluation board accepts a 1 V input signal centered at
ground. T he board’s input circuitry then biases this signal to
+2.5 V in one of two ways:
1. DC-coupled through an AD9631 op amp; this is the mode in
which it is shipped. Potentiometer R7 provides adjustment
of the bias voltage.
2. AC-coupled through C1.
T hese two modes are selected by jumpers S101 and S103. For
dc coupling, the S101 jumper is connected between the two left
pins and the S103 jumper is connected between the two lower
pins. For ac coupling, the S101 jumper is connected between
the two right pins and the S103 jumper is connected between
the two upper pins.
E NC ODE
T he AD9054 ENCODE input can be driven two ways:
1. Differential T T L, CMOS, or PECL; it is shipped in this
mode.
2. Single-ended T T L or CMOS. T o use in this mode, remove
R11, the 50
chip resistor located next to the
ENCODE
input, and insert a 0.1
μ
F ceramic capacitor into the C5 slot.
C5 is located between the ENC connector and the ENCODE
input to the DUT and is marked on the back side of the
board. In this mode,
ENCODE
is biased with internal resis-
tors to 1.5 V, but it can be externally driven to any dc voltage.
Voltage Reference
T he AD9054 has an internal 2.5 V voltage reference. An exter-
nal reference may be employed instead. T he evaluation board is
configured for the internal reference. T o use an external refer-
ence, connect it to the (VREF) pin on the power connector and
move jumper S102.
Single Port Mode
Single Port Mode sets the AD9054 to produce data on every
clock cycle on output port A only. T o test in this mode, jumper
S104 should be set to single channel and S106 and S107 must
be set to F (for Full). T he maximum speed in single port mode
is 100 MSPS.
Dual Port Mode
Dual Port or half speed output mode sets the ADC to produce
data alternately on Port A and Port B. In this mode, the reset
function should be implemented. T o test in this mode, set
jumper S104 to Dual Channel, and set S106 and S107 to D (for
Dual Port). T he maximum speed in this mode is 200 MSPS.
RE SE T
RESET drives the AD9054’s Data Sync (DS) pins. When
operating in Single Port Mode, RESET is not used. In Dual-
Channel Mode it is needed for two reasons: to synchronize the
timing of Port A data and Port B data with a known clock edge,
as described in the data sheet, and to synchronize the evaluation
board’s latch clocks with the data coming out of the AD9054.
Reset can be driven in two ways: by pushing the reset button on
the board, or externally, with a T T L pulse through connector J5
or J6.
DAC Out
T he DAC output is a representation of the data on output Port
A only. Output Port B is not reconstructed.
T roubleshooting
If the board does not seem to be working correctly, try the fol-
lowing:
Check that all jumpers are in the correct position for the
desired mode of operation.
Push the reset button. T his will align the 9054’s data output
with the half speed latch clocks.
Switch the jumper S105 from A-R to R-B or vice-versa, then
push the reset button. In demuxed mode, this will have the
effect of inverting the half speed latch clocks.
At high encode rates, the evaluation board’s clock generation
circuitry is sensitive to the +5 V digital power supply. At
high encode rates, the +5 V digital power should be kept
below +5.2 V. T his is an evaluation board sensitivity and
not an AD9054 sensitivity.
T he AD9054 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warran-
ties, express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9054BST-135 | 8-Bit, 200 MSPS A/D Converter |
| AD9054BST-200 | 8-Bit, 200 MSPS A/D Converter |
| AD9054PCB | 8-Bit, 200 MSPS A/D Converter |
| AD9057 | 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| AD9057BRS-80 | 8-Bit 40 MSPS/50 MSPS/80 MSPS Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9054/PCB | 制造商:Analog Devices 功能描述:TEST BOARD AD9054 |
| AD9054A | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit, 200 MSPS A/D Converter |
| AD9054A/PCB | 制造商:Analog Devices 功能描述:8B 200 MSPS ADC - EVAL BORD. - Bulk |
| AD9054ABST-135 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 135Msps 8-bit Parallel 44-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:8B 135 MSPS ADC - Bulk |
| AD9054ABST-200 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 200Msps 8-bit Parallel 44-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:8B 200 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
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