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参数资料
| 型号： | AD9054BST-135 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 8-Bit, 200 MSPS A/D Converter |
| 中文描述： | 2-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封装： | PLASTIC, TQFP-44 |
| 文件页数： | 11/20页 |
| 文件大小： | 303K |
| 代理商： | AD9054BST-135 |
AD9054
–11–
REV. 0
APPLICAT ION NOT E S
T HE ORY OF OPE RAT ION
T he AD9054 combines Analog Devices’ patented MagAmp bit-
per-stage architecture with flash converter technology to create
a high performance, low power ADC. For ease of use the part
includes an onboard reference and input logic that accepts
T T L, CMOS or PECL levels.
T he analog input signal is buffered by a high-speed differential
amplifier and applied to a track-and-hold (T /H) circuit. T his
T /H captures the value of the input at the sampling instant and
maintains it for the duration of the conversion. T he sampling
and conversion process is initiated by a rising edge on the
ENCODE input. Once the signal is captured by the T /H, the
four Most Significant Bits (MSBs) are sequentially encoded by
the MagAmp string. T he residue signal is then encoded by a
flash comparator string to generate the four Least Significant
Bits (LSBs). T he comparator outputs are decoded and com-
bined into the eight-bit result.
If the user has selected Single Channel Mode (
DEMUX
=
HIGH), the eight-bit data word is directed to the Channel A
output bank. Data are strobed to the output on the rising edge
of the ENCODE input with four pipeline delays. If the user has
selected Dual Channel Mode (
DEMUX
= LOW) the data are
alternately directed between the A and B output banks and have
five pipeline delays. At power-up, the N sample data can ap-
pear at either the A or B port. T o align the data in a known
state the user must strobe DAT A SYNC (DS,
DS
) per the
conditions described in the T iming section.
Graphics Applications
T he high bandwidth and low power of the AD9054 make it
very attractive for applications that require the digitization of
presampled waveforms, wherein the input signal rapidly slews
from one level to another and is relatively stable for a period of
time. Examples of these include digitizing the output of com-
puter graphic display systems and very high speed solid state
imagers.
T hese applications require the converter to process inputs with
frequency components well in excess of the sampling rate (often
with subnanosecond rise times), after which the A/D must settle
and sample the input in well under one pixel time. T he archi-
tecture of the AD9054 is vastly superior to older flash architec-
tures, which not only exhibit excessive input capacitance (which
is very hard to drive) but can make major errors when fed a very
rapidly slewing signal. T he AD9054’s extremely wide bandwidth
T rack/Hold circuit processes these signals without difficulty.
Using the AD9054
Good high speed design practices must be followed when using
the AD9054. T o obtain maximum benefit, decoupling capaci-
tors should be physically as close to the chip as possible. We
recommend placing a 0.1
μ
F capacitor at each power-ground
pin pair (9 total) for high frequency decoupling, and including
one 10
μ
F capacitor for local low frequency decoupling. T he
VREF IN pin should also be decoupled by a 0.1
μ
F capacitor.
T he part should be located on a solid ground plane and output
trace lengths should be short (<1 inch) to minimize transmis-
sion line effects. T his avoids the need for termination resistors
on the output bus and reduces the load capacitance that needs
to be driven, which in turn minimizes on-chip noise due to
heavy current flow in the outputs. We have obtained optimum
performance on our evaluation board by tying all V
DD
pins to a
quiet analog power supply system, and tying all GND pins to a
quiet analog system ground.
Minimum E ncode Rate
T he minimum sampling rate for the AD9054 is 25 MHz. T o
achieve very high sampling rates, the track/hold circuit employs
a very small hold capacitor. When operated below the minimum
guaranteed sampling rate, the T /H droop becomes excessive.
T his is first observed as an increase in offset voltage, followed by
degraded linearity at even lower frequencies.
Lower effective sampling rates may be easily supported by oper-
ating the converter in dual port output mode and using only one
output channel. A majority of the power dissipated by the AD9054
is static (not related to conversion rate) so the penalty for clock-
ing at twice the desired rate is not high.
Reference
T he AD9054 internal reference, VREF, provides a simple, cost
effective reference for many applications. It exhibits reasonable
accuracy and excellent stability over power supply and tempera-
ture variations. T he VREF OUT pin can simply be strapped to
the VREF IN pin. T he internal reference can be used to drive
additional loads (up to several mA), including multiple A/D con-
verters as might be required in a triple video converter application.
When an external reference is desired for accuracy or other
requirements, the AD9054 should be driven directly by the
external reference source connected to pin VREF IN (VREF
OUT can be left floating). T he external reference can be set to
2.5 V
±
0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the
analog full-scale range will increase by 10% to 1.024
×
1.1 =
1.1264 V. T he new input range will then be
AIN
±
0.5632 V.
Digital Inputs
SNR performance is directly related to the sampling clock sta-
bility in A/D converters, particularly for high input frequencies
and wide bandwidths. A low jitter clock (<10 ps @ 100 MHz)
is essential for optimum performance when digitizing signals
that are not presampled.
ENCODE and Data Select (DS) can be driven differentially or
single-ended. For single-ended operation, the complement
inputs (
ENCODE
,
DS
) are internally biased to V
DD
/3 (~1.5 V)
by a high impedance on-chip resistor divider (Figure 5), but
they may be externally driven to establish an alternate threshold
if desired. A 0.1
μ
F decoupling capacitor to ground is sufficient
to maintain a threshold appropriate for T T L or CMOS logic.
T
AMB
–
8
C
V
2.502
2.501
2.498
–40
100
–20
0
20
40
60
80
2.500
2.499
Figure 33. Reference Voltage vs. Temperature
相关PDF资料 |
PDF描述 |
|---|---|
| AD9054BST-200 | 8-Bit, 200 MSPS A/D Converter |
| AD9054PCB | 8-Bit, 200 MSPS A/D Converter |
| AD9057 | 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| AD9057BRS-80 | 8-Bit 40 MSPS/50 MSPS/80 MSPS Converter |
| AD9057BRS-40 | 8-Bit 40 MSPS/50 MSPS/80 MSPS Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9054BST-200 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit, 200 MSPS A/D Converter |
| AD9054PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit, 200 MSPS A/D Converter |
| AD9057 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| AD9057/PCB | 制造商:Analog Devices 功能描述:EVAL KIT FOR ADC, 8BIT 40MSPS/60MSPS/80MSPS A/D CNVRTR - Bulk |
| AD9057_03 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
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