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参数资料
| 型号： | AD9058 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | ADC |
| 英文描述： | Dual 8-Bit 50 MSPS A/D Converter |
| 中文描述： | 双8位50 MSPS的A/D转换 |
| 文件页数： | 6/8页 |
| 文件大小： | 148K |
| 代理商： | AD9058 |
REV. B
AD9058
–6–
18
17
16
15
14
13
12
11
RZ1
28
29
30
31
32
33
34
35
ANALOG
IN B
±0.125 V
AD9618
+
400
50
5k
ANALOG
±IN A
AD580
1
3
2
10k
10k
0.1μF
1/2
AD708
–
+5V
+5V
20k
+V
REF A
ENCODE
A
ENCODE
B
AD9618
+
400
50
A1/2
+
5
20k
3
43
8
38
10
150
150
10
10pF
1k
50k
5, 9, 22,
24, 37, 41
+5V
RZ2
D
0A
(LSB)
D
7A
(MSB)
D
0B
(LSB)
D
7B
(MSB)
8
7
8
7
CLOCK
CLOCK
–
V
S
7, 20,
26, 39
0.1μF
1N4001
4,19, 21
25, 27, 42
RZ1, RZ2 = 2,000
SIP (8/PKG)
ENCODE
10
36
2N3904
0.1μF
0.1μF
+1V
±1V
–
1V
2N3906
±1 V
0.1μF
COMP
1
0.1μF
6
40
AD9058
(J-LEAD)
74ACT04
5V
–
+
–
–
–
5V
–
(SEE TEXT)
+V
REF B
A
IN A
–
V
REF A
–
V
REF B
A
IN B
+V
S
Figure 3. AD9058 Using External Voltage References
The AD9058 offers considerable flexibility in selecting the ana-
log input ranges of the ADCs; the two independent ADCs can
even have different input ranges if required. In Figure 3 above,
the AD9058 is shown configured for
±
1 V operation.
The
Reference Ladder Offset
shown in the specifications table re-
fers to the error between the voltage applied to the +V
REF
(top)
or –V
REF
(bottom) of the reference ladder and the voltage re-
quired at the analog input to achieve a 1111 1111 or 0000 0000
transition. This indicates the amount of adjustment range which
must be designed into the reference circuit for the AD9058.
The diode shown between ground and –V
S
is normally reverse
biased and is used to prevent latch-up. Its use is recommended
for applications in which power supply sequencing might allow
+V
S
to be applied before –V
S
; or the +V
S
supply is not current
limited. If the negative supply is allowed to float (the +5 V sup-
ply is powered up before the –5 V supply), substantial +5 V
supply current will attempt to flow through the substrate (V
S
supply contact) to ground. If this current is not limited to <500
mA, the part may be destroyed. The diode prevents this poten-
tially destructive condition from occurring.
Timing
Refer to the AD9058 Timing Diagram. The AD9058 provides
latched data outputs with no pipeline delay. To conserve power,
the data outputs have relatively slow rise and fall times. When
designing system timing, it is important to observe (1) set-up
and hold times; and (2) the intervals when data is changing.
Figure 3 shows 2 k
pull-down resistors on each of the D
0
–D
7
output data bits. When operating at conversion rates higher than
40 MSPS, these resistors help equalize rise and fall times and
ease latching the output data into external latches. The 74ACT
logic family devices have short set-up and hold times and are the
recommended choices for speeds of 40 MSPS or more.
Layout
To insure optimum performance, a single low-impedance ground
plane is recommended. Analog and digital grounds should be
connected together and to the ground plane at the AD9058 de-
vice. Analog and digital power supplies should be bypassed to
ground through 0.1
μ
F ceramic capacitors as close to the unit as
possible.
An evaluation board (ADI part #AD9058/PCB) is available to
aid designers and provide a suggested layout. The use of sockets
may limit the dynamic performance of the part and is not rec-
ommended except for prototype or evaluation purposes.
For prototyping or evaluation, surface mount sockets are available
from Methode (part #213-0320602) for evaluating AD9058 sur-
face mount packages. To evaluate the AD9058 in through-hole
PCB designs, use the AD9058JD/KD with individual pin sockets
(AMP part #6-330808-0). Alternatively, surface mount AD9058
units can be mounted in a through-hole socket (Circuit Assembly
Corporation, Irvine California part #CA-44SPC-T).
AD9058 APPLICATIONS
Combining two ADCs in a single package is an attractive alter-
native in a variety of systems when cost, reliability and space are
important considerations. Different systems emphasize particu-
lar specifications, depending on how the part is used.
In high density digital radio communications, a pair of high
speed ADCs are used to digitize the in-phase (I) and quadrature
(Q) components of a modulated signal. The signal presented to
each ADC in this type of system consists of message-dependent
amplitudes varying at the symbol rate, which is equal to the
sample rates of the converters.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9058KD | Dual 8-Bit 50 MSPS A/D Converter |
| AD9059PCB | Dual 8-Bit, 60 MSPS A/D Converter |
| AD9059 | Dual 8-Bit, 60 MSPS A/D Converter |
| AD9059BRS | Dual 8-Bit, 60 MSPS A/D Converter |
| AD9060KZ | 10-Bit 75 MSPS A/D Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9058-803D | 制造商:Analog Devices 功能描述:- Rail/Tube |
| AD9058AJD | 功能描述:IC ADC 8BIT DUAL 50MSPS 48-CDIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9058AJJ | 功能描述:IC ADC 8BIT DUAL 50MSPS 44-JLCC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9058AJJ-REEL | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 8-Bit 50 MSPS A/D Converter |
| AD9058AKD | 功能描述:IC ADC 8BIT DUAL 50MSPS 48-CDIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
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