参数资料
| 型号： | AD9117BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/52页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 14BIT LO PWR 40LFCSP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 设计资源： | High CMRR Circuit for Converting Wideband Complementary DAC Outputs to Single-Ended Without Precision Resistors (CN0142) |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| 位数： | 14 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 232mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 125M |
| 产品目录页面： | 785 (CN2011-ZH PDF) |
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Data Sheet
AD9114/AD9115/AD9116/AD9117
Rev. C | Page 33 of 52
SERIAL PERIPHERAL INTERFACE (SPI)
The serial port of the AD9114/AD9115/AD9116/AD9117 is a
flexible, synchronous serial communications port that allows easy
interfacing to many industry-standard microcontrollers and micro-
processors. The serial I/O is compatible with most synchronous
transfer formats, including both the Motorola SPI and Intel SSR
protocols. The interface allows read/write access to all registers
that configure the AD9114/AD9115/AD9116/AD9117. Single or
multiple byte transfers are supported, as well as MSB first or
LSB first transfer formats. The serial interface port of the AD9114/
AD9115/AD9116/AD9117 is configured as a single I/O pin on
the SDIO pin.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle on the AD9114/
AD9115/AD9116/AD9117. Phase 1 is the instruction cycle, which
is the writing of an instruction byte into the AD9114/AD9115/
AD9116/AD9117, coinciding with the first eight SCLK rising
edges. In Phase 2, the instruction byte provides the serial port
controller of the AD9114/AD9115/AD9116/AD9117 with infor-
mation regarding the data transfer cycle. The Phase 1 instruction
byte defines whether the upcoming data transfer is a read or write,
the number of bytes in the data transfer, and the starting register
address for the first byte of the data transfer. The first eight SCLK
rising edges of each communication cycle are used to write the
instruction byte into the AD9114/AD9115/AD9116/AD9117.
A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0,
resets the SPI port timing to the initial state of the instruction
cycle. This is true regardless of the present state of the internal
registers or the other signal levels present at the inputs to the
SPI port. If the SPI port is in the midst of an instruction cycle
or a data transfer cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9114/
AD9115/AD9116/AD9117 and the system controller. Phase 2
of the communication cycle is a transfer of one, two, three, or
four data bytes, as determined by the instruction byte. Using a
multibyte transfer is the preferred method. Single byte
data transfers are useful to reduce CPU overhead when register
access requires one byte only. Registers change immediately
upon writing to the last bit of each transfer byte.
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 11.
Table 11.
MSB
LSB
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W
N1
N0
A4
A3
A2
A1
A0
R/W (Bit 7 of the instruction byte) determines whether a read or a
write data transfer occurs after the instruction byte write. Logic 1
indicates a read operation. Logic 0 indicates a write operation.
N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the
number of bytes to be transferred during the data transfer cycle.
The bit decodes are shown in Table 12.
Table 12. Byte Transfer Count
N1
N0
Description
0
Transfer 1 byte
0
1
Transfer 2 bytes
1
0
Transfer 3 bytes
1
Transfer 4 bytes
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte) determine which register is accessed during the
data transfer portion of the communications cycle. For multi-
byte transfers, this address is the starting byte address. The
following register addresses are generated internally by the
AD9114/AD9115/AD9116/AD9117 based on the LSBFIRST bit
(Register 0x00, Bit 6).
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9114/AD9115/AD9116/AD9117 and to run the internal state
machines. The SCLK maximum frequency is 25 MHz. All data
input to the AD9114/AD9115/AD9116/AD9117 is registered on
the rising edge of SCLK. This is shown in Figure 85 and Figure 87
for write instructions where the SCLK rising edges are lined up in
the middle of the data. All data is driven out of the AD9114/AD9115/
AD9116/AD9117 on the falling edge of SCLK. This is shown in
Figure 86 and Figure 88 for read cycles where the SCLK falling
edges line up in the middle of the data in the data transfer cycle.
CS—Chip Select
An active low input starts and gates a communications cycle. It
allows more than one device to be used on the same serial commu-
nications lines. The SDIO/FORMAT pin reaches a high impedance
state when this input is high. Chip select should stay low during
the entire communication cycle.
SDIO—Serial Data I/O
The SDIO pin is used as a bidirectional data line to transmit
and receive data.
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| AD9117BCPZN | 功能描述:数模转换器- DAC Dual 14B Low Power D-A Converter RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| AD9117BCPZNRL7 | 功能描述:数模转换器- DAC Dual Low Pwr 14-Bit RoHS:否 制造商:Analog Devices 转换器数量:4 DAC 输出端数量:4 转换速率: 分辨率:12 bit 接口类型:Serial (I2C) 稳定时间: 最大工作温度:+ 105 C 安装风格: 封装 / 箱体:TSSOP 封装:Reel |
| AD9117BCPZRL7 | 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD9117-DPG2-EBZ | 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9117-EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9117, DUAL, 8-/10-/12-/14BIT LOW PWR DGTL-TO-A - Boxed Product (Development Kits) |
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