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| 型号： | AD9215BCP-65EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9215BCP-65 |
| 设计资源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) Interfacing the High Frequency AD8331 to AD9215 (CN0096) |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 65M |
| 数据接口： | 并联 |
| 输入范围： | 1 Vpp |
| 在以下条件下的电源（标准）： | 96mW @ 65MSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9215-65 |
| 已供物品： | 板 |
| 相关产品： | AD9215BRUZ-80-ND - IC ADC 10BIT 80MSPS 3V 28TSSOP AD9215BRUZ-65-ND - IC ADC 10BIT 65MSPS 3V 28TSSOP AD9215BRUZRL7-105-ND - IC ADC 10BIT 105MSPS 3V 28TSSOP AD9215BRUZRL7-65-ND - IC ADC 10BIT 65MSPS 3V 28TSSOP AD9215BRUZRL7-80-ND - IC ADC 10BIT 80MSPS 3V 28TSSOP AD9215BRUZ-105-ND - IC ADC 10BIT 105MSPS 3V 28-TSSOP AD9215BCPZ-105-ND - IC ADC 10BIT 105MSPS 3V 32-LFCSP AD9215BRU-105-ND - IC ADC 10BIT 105MSPS 3V 28-TSSOP AD9215BCPZ-80-ND - IC ADC 10BIT 80MSPS 32LFCSP AD9215BCPZ-65-ND - IC ADC 10BIT 65MSPS 32-LFCSP 更多... |
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AD9215
Data Sheet
Rev. B | Page 14 of 36
APPLYING THE AD9215 THEORY OF OPERATION
The AD9215 architecture consists of a front-end SHA followed
by a pipelined switched capacitor ADC. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 10-bit result in the digital correction logic. The pipe-
lined architecture permits the first stage to operate on a new
input sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
The input stage contains a differential SHA that can be config-
ured as ac-coupled or dc-coupled in differential or single-ended
modes. Each stage of the pipeline, excluding the last, consists of
a low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipe-
line. Redundancy is used in each one of the stages to facilitate
digital correction of flash errors.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjust-
ment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
Analog Input and Reference Overview
The analog input to the AD9215 is a differential switched
capacitor SHA that has been designed for optimum perfor-
mance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance, as shown in Figure 31. An input com-
mon-mode voltage of midsupply minimizes signal-dependent
errors and provides optimum performance.
02874-A-028
H
VIN+
VIN–
CPAR
T
0.5pF
T
Figure 30. Switched-Capacitor SHA Input
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 30). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s in-
put; therefore, the precise values are dependent upon the appli-
cation. In IF undersampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance, they would limit the input bandwidth.
The analog inputs of the AD9215 are not internally dc biased.
In ac-coupled applications, the user must provide this bias ex-
ternally. VCM = AVDD/2 is recommended for optimum perfor-
mance, but the device functions over a wider range with rea-
sonable performance (see Figure 31).
02874-A-071
40
45
50
55
60
65
70
75
80
85
0.25
0.75
1.25
1.75
2.25
2.75
dB
ANALOG INPUT COMMON-MODE VOLTAGE (V)
2V p-p SFDR
2V p-p SNR
Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed val-
ues of 0.5 V or 1.0 V or adjusted within the same range as dis-
cussed in the Internal Reference Connection section. Maximum
SNR performance is achieved with the AD9215 set to the largest
input span of 2 V p-p. The relative SNR degradation is 3 dB
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