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参数资料
| 型号： | AD9215BCPZ-65 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | Circular Connector; No. of Contacts:15; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 |
| 中文描述： | 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封装： | MO-220-VHHD-2, LEAD FREE, LFCSP-32 |
| 文件页数： | 18/36页 |
| 文件大小： | 1416K |
| 代理商： | AD9215BCPZ-65 |
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AD9215
Rev. A | Page 18 of 36
0
I
LOAD
(mA)
V
0
0.05
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
VREF = 0.5V
VREF = 1.0V
Figure 38. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. When multiple ADCs track one another, a single refer-
ence (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 39 shows the typical drift characteris-
tics of the internal reference in both 1 V and 0.5 V modes.
0
TEMPERATURE (
°
C)
V
0.4
0.5
0.6
0.3
0.2
0.1
0
–40
–20
0
20
40
60
80
VREF = 1.0V
VREF = 0.5V
Figure 39. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 k load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
Operational Mode Selection
As discussed earlier, the AD9215 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock duty cycle stabilizer (DCS). The
MODE pin is a multilevel input that controls the data format
and DCS state. For best ac performance, enabling the duty cycle
stabilizer is recommended for all applications. The input
threshold values and corresponding mode selections are out-
lined in Table 9.
As detailed in Table 9, the data format can be selected for either
offset binary or twos complement.
Table 9. Mode Selection
MODE Voltage
Data Format
AVDD
Twos Complement
2/3 AVDD
Twos Complement
1/3 AVDD
Offset Binary
AGND (Default)
Offset Binary
Duty Cycle Stabilizer
Disabled
Enabled
Enabled
Disabled
The MODE pin is internally pulled down to AGND by a 20 k
resistor.
EVALUATION BOARD
The AD9215 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially
through an AD8351 driver, a transformer, or single-ended.
Separate power pins are provided to isolate the DUT from the
support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 40 shows the typical bench characterization setup used
to evaluate the ac performance of the AD9215. It is critical that
signal sources with very low phase noise (<1 ps rms jitter) be
used to realize the ultimate performance of the converter.
Proper filtering of the input signal, to remove harmonics and
lower the integrated noise at the input, is also necessary to
achieve the specified noise performance.
Complete schematics and layout plots follow that demonstrate
the proper routing and grounding techniques that should be
applied at the system level.
0
R AND S SMG, 2V p-p
SIGNAL SYNTHESIZER
R AND S SMG, 2V p-p
SIGNAL SYNTHESIZER
REFIN
10MHz
REFOUT
BAND-PASS
FILTER
3.0V
–
+
–
+
–
+
–
+
2.5V
5.0V
AVDD
DRVDD
GND
GND V
DL
VAMP
XFMR
INPUT
CLK
P12
AD9215
EVALUATION BOARD
DATA
CAPTURE
AND
PROCESSING
2.5V
Figure 40. Evaluation Board Connections
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