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参数资料
| 型号： | AD9216BCPZRL7-105 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| 中文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC64 |
| 封装： | 9 X 9 MM, LEAD FREE, MO-220-VMMD, LFCSP-64 |
| 文件页数： | 16/20页 |
| 文件大小： | 298K |
| 代理商： | AD9216BCPZRL7-105 |
AD9216
Preliminary Technical Data
The data format can be selected for either offset binary or twos
complement. This is discussed later in the Data Format section.
Rev. PrD
Page 16 of 20
6/15/2004
TIMING
The AD9216 provides latched data outputs with a pipeline
delay of six clock cycles. Data outputs are available one
propagation delay (t
) after the rising edge of the clock signal.
Refer to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the
AD9216 using the DCS pin. This provides a stable 50% duty
cycle to internal circuits.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9216.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9216
is 1 MSPS. At clock rates below 1 MSPS, dynamic
performance may degrade.
Figure 6.
NEEDS UPDATING
Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and
MUX_SELECT
DATA FORMAT
The AD9216 data output format can be configured for either
twos complement or offset binary. This is controlled by the
Data Format Select pin (DFS). Connecting DFS to AGND will
produce offset binary output data. Conversely, connecting DFS
to AVDD will format the output data as twos complement.
The output data from the dual A/D converters can be
multiplexed onto a single 10-Bits output bus. The multiplexing
is accomplished by toggling the MUX_SELECT bit, which
directs channel data to the same or opposite channel data port.
When MUX_SELECT is logic high, the Channel A data is
directed to Channel A output bus, and Channel B data is
directed to the Channel B output bus. When MUX_SELECT is
logic low, the channel data is reversed, i.e., Channel A data is
directed to the Channel B output bus and Channel B data is
directed to the Channel A output bus. By toggling the
MUX_SELECT bit, multiplexed data is available on either of
the output data ports.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT bit. After the
MUX_SELECT rising edge, either data port will have the data
for its respective channel; after the falling edge, the alternate
channel’s data will be placed on the bus. Typically, the other
unused bus would be disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 6 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel's power-
down pin must remain low.
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相关代理商/技术参数 |
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| AD9216BCPZRL7-65 | 功能描述:IC ADC 10BIT DUAL 65MSPS 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD9216BCPZRL7-80 | 功能描述:IC ADC 10BIT DUAL 80MSPS 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD9218 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
| AD9218_06 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 40/65/80/105 MSPS 3 V Dual Analog-to-Digital Converter |
| AD9218-105PCB | 制造商:Analog Devices 功能描述:DUAL 10 BIT 105/80/65 MSPS ADC EVAL BD. - Bulk |
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