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参数资料
| 型号： | AD9216BCPZRL7-80 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| 中文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC64 |
| 封装： | 9 X 9 MM, LEAD FREE, MO-220-VMMD, LFCSP-64 |
| 文件页数： | 15/20页 |
| 文件大小： | 298K |
| 代理商： | AD9216BCPZRL7-80 |
Preliminary Technical Data
AD9216
cost-sensitive applications. In this configuration, there will be a
degradation in SFDR and in distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
Rev. PrD
Page 15 of 20
6/15/2004
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9216 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels
asynchronously may degrade performance significantly. In
some applications, it is desirable to skew the clock timing of
adjacent channels. The AD9216’s separate clock inputs allow
for clock timing skew (typically ±1 ns) between the channels
without significant performance degradation.
The AD9216 contains two clock duty cycle stabilizers, one for
each converter, that retime the non-sampling edge, providing an
internal clock with a nominal 50% duty cycle. Faster Input
clock rates (where it becomes difficult to maintain 50% duty
cycles) can benefit from using DCS as a wide range of input
clock duty cycles can be accommodated. Maintaining a 50%
duty cycle clock is particularly important in high speed
applications, when proper track-and-hold times for the
converter are required to maintain high performance. The DCS
can be enabled by tying the DCS pin high.
The duty cycle stabilizer utilizes a delay locked loop to create
the non-sampling edge. As a result, any changes to the
sampling frequency will require approximately 2 μs to 3 μs to
allow the DLL to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
INPUT
) due only to aperture jitter (t
J
) can be
calculated
with the following equation:
[
]
J
t
f
p
2
1
10
20
radation
SNR
INPUT
×
×
×
×
=
log
deg
In the equation, the rms aperture jitter, t
J
, represents the root-
sum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Under-sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture
jitter may affect the dynamic range of the AD9216, it is
important to minimize input clock jitter. The clock input
circuitry should use stable references, for example using analog
power and ground planes to generate the valid high and low
digital levels for the AD9216 clock input. Power supplies for
clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9216 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
N
f
C
V
I
CLOCK
LOAD
DRVDD
DRVDD
×
×
×
=
where N is the number of bits changing and C
LOAD
is the
average load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9216 can be placed into standby mode
independently by asserting the PWDN_A or PDWN_B pins.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
will result in a typical power consumption of 1 mW for the
ADC. Note that if DCS is enabled, it is mandatory to disable
the clock of an independently powered-down channel.
Otherwise, significant distortion will result on the active
channel. If the clock inputs remain active while in total standby
mode, typical power dissipation of TBD mW will result.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B
= HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time will be directly related to
the recharging of the REFT and REFB decoupling capacitors
and to the duration of the power-down. Typically, it takes
approximately 5 ms to restore full operation with fully
discharged 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB.
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered. Because the buffer and voltage reference
remain powered, the wake-up time is reduced to several clock
cycles.
DIGITAL OUTPUTS
The AD9216 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the
digital supply of the interfaced logic. The output drivers are
sized to provide sufficient output current to drive a wide variety
of logic families. However, large drive currents tend to cause
current glitches on the supplies that may affect converter
performance. Applications requiring the ADC to drive large
capacitive loads or large fan-outs may require external buffers
or latches.
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