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| 型号： | AD9221ARS-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 1.5MSPS 28-SSOP |
| 标准包装： | 1,500 |
| 位数： | 12 |
| 采样率（每秒）： | 1.5M |
| 数据接口： | 并联 |
| 转换器数目： | 7 |
| 功率耗散（最大）： | 70mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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REV. E
–18–
AD9221/AD9223/AD9220
FREQUENCY – MHz
–55
–95
1
100
10
SFDR
–
dB
–65
–75
–85
AD9221
AD9223
AD9220
Figure 18. AD9221/AD9223/AD9220 SFDR vs. Input
Frequency (VCM = 2.5 V, 2 V p-p Input Span,
AIN = –0.5 dB)
Figure 19 shows the schematic of the suggested transformer
circuit. The circuit uses a Mini-Circuits RF transformer, model
#T4-6T, which has an impedance ratio of 4 (turns ratio of 2).
The schematic assumes that the signal source has a 50
source
impedance. The 1:4 impedance ratio requires the 200
sec-
ondary termination for optimum power transfer and VSWR.
The center tap of the transformer provides a convenient means
of level shifting the input signal to a desired common-mode
voltage. Optimum performance can be realized when the center
tap is tied to CML of the AD9221/AD9223/AD9220, which is
the common-mode bias level of the internal SHA.
VINA
VINB
AD9221/
AD9223/
AD9220
200
49.9
RS
33
CML
CS
15pF
MINI-CIRCUITS
T4-1
0.1 F
RS
33
CS
15pF
Figure 19. Transformer Coupled Input
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example, a
given input signal source or amplifier may realize an improve-
ment in distortion performance at reduced output power levels
and signal swings. Therefore, selecting a transformer with a
higher impedance ratio (e.g., Mini-Circuits T16-6T with a 1:16
impedance ratio) effectively “steps up” the signal level, thus
further reducing the driving requirements of the signal source.
Referring to Figure 19, a series resistor, RS, and shunt capacitor,
CS, were inserted between the AD9221/AD9223/AD9220 and
the secondary of the transformer. The values of 33
and 15 pF
were selected to specifically optimize both the THD and SNR
performance of the A/D. RS and CS help provide some isola-
tion from transients at the A/D inputs reflected back through the
primary of the transformer.
The AD9221/AD9223/AD9220 can be easily configured for
either a 2 V p-p input span or 5.0 V p-p input span by setting
the internal reference (see Table II). Other input spans can be
realized with two external gain setting resistors as shown in
Figure 23 of this data sheet. Figure 20 demonstrates how both
spans of the AD9220 achieve the high degree of linearity and
SFDR over a wide range of amplitudes required by the most
demanding communication applications. Similar performance is
achievable with the AD9221 and AD9223 at their correspond-
ing Nyquist frequency.
INPUT AMPLITUDE – dBFS
90
20
–50
0
SNR/SFDR
–
dB
–40
–30
–20
–10
80
70
30
60
50
40
SNR – 2.0V p-p
SNR – 5.0V p-p
SFDR – 5.0V p-p
SFDR – 2.0V p-p
Figure 20. AD9220 SFDR, SNR vs. Input Amplitude
(fIN = 5 MHz, fCLK = 10 MSPS, VCM = 2.5 V, Differential)
Figure 20 also reveals a noteworthy difference in the SFDR and
SNR performance of the AD9220 between the 2 V p-p and 5 V p-p
input span options. First, the SNR performance improves by 2 dB
with a 5.0 V p-p input span due to the increase in dynamic
range. Second, the SFDR performance of the AD9220 will
improve for input signals below approximately –6.0 dBFS. A 3 dB
to 5 dB improvement was typically realized for input signal levels
between –6.0 dBFS and –36 dBFS. This improvement in SNR
and SFDR for a 5.0 V p-p span may be advantageous for com-
munication systems that have additional margin or headroom
to minimize clipping of the ADC.
REFERENCE CONFIGURATIONS
The figures associated with this section on internal and external
reference operation do not show recommended matching series resistors
for VINA and VINB for the purpose of simplicity. Please refer to the
Driving the Analog Inputs, Introduction section for a discussion of
this topic. Also, the figures do not show the decoupling network asso-
ciated with the CAPT and CAPB pins. Please refer to the Reference
Operation section for a discussion of the internal reference circuitry
and the recommended decoupling network shown in Figure 10.
USING THE INTERNAL REFERENCE
Single-Ended Input with 0 to 2
VREF Range
Figure 21 shows how to connect the AD9221/AD9223/AD9220
for a 0 V to 2 V or 0 V to 5 V input range via pin strapping the
SENSE pin. An intermediate input range of 0 to 2
× VREF can
be established using the resistor programmable configuration in
Figure 23 and connecting VREF to VINB.
In either case, both the common-mode voltage and input span
are directly dependent on the value of VREF. More specifically,
the common-mode voltage is equal to VREF while the input
span is equal to 2
× VREF. Thus, the valid input range extends
from 0 to 2
× VREF. When VINA is ≤ 0 V, the digital output
will be 000 Hex; when VINA is
≥ 2 × VREF, the digital output
will be FFF Hex.
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