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参数资料
| 型号： | AD9223 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 串行ADC |
| 英文描述： | Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters |
| 中文描述： | 完整的12位1.5/3.0/10.0 MSPS的单片的A / D转换器 |
| 文件页数： | 11/28页 |
| 文件大小： | 350K |
| 代理商： | AD9223 |
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AD9221/AD9223/AD9220
REV. D
–11–
Referring to Figure 32, the differential SHA is implemented
using a switched-capacitor topology. Hence, its input imped-
ance and its subsequent effects on the input drive source should
be understood to maximize the converter’s performance. The
combination of the pin capacitance, C
PIN
, parasitic capacitance
C
PAR,
and the sampling capacitance, C
S
, is typically less than
16 pF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on C
S
to the new
input voltage. This action of charging and discharging C
S
,
averaged over a period of time and for a given sampling fre-
quency, F
S
, makes the input impedance appear to have a benign
resistive component. However, if this action is analyzed within
a sampling period (i.e., T = 1/F
S
), the input impedance is dy-
namic and hence certain precautions on the input drive source
should be observed.
The resistive component to the input impedance can be com-
puted by calculating the average charge that gets drawn by C
H
from the input drive source. It can be shown that if C
S
is al-
lowed to fully charge up to the input voltage before switches Q
S1
are opened, then the average current into the input is the same
as if there were a resistor of 1/(C
S
F
S
) ohms connected between
the inputs. This means that the input impedance is inversely
proportional to the converter’s sample rate. Since C
S
is only
4 pF, this resistive component is typically much larger than that
of the drive source (i.e., 25 k
at F
S
= 10 MSPS).
If one considers the SHA’s input impedance over a sampling
period, it appears as a dynamic input impedance to the input
drive source. When the SHA goes into the track mode, the
input source should ideally provide the charging current through
R
ON
of switch Q
S1
in an exponential manner. The requirement
of exponential charging means that the most common input
source, an op amp, must exhibit a source impedance that is both
low and resistive up to and beyond the sampling frequency.
The output impedance of an op amp can be modeled with a
series inductor and resistor. When a capacitive load is switched
onto the output of the op amp, the output will momentarily
drop due to its effective output impedance. As the output re-
covers, ringing may occur. To remedy the situation, a series
resistor can be inserted between the op amp and the SHA input
as shown in Figure 33. The series resistance helps isolate the op
amp from the switched-capacitor load.
10
m
F
VINA
VINB
SENSE
AD9221/AD9223/
AD9220
0.1
m
F
R
S
V
CC
V
EE
R
S
VREF
REFCOM
Figure 33. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several factors
which include the AD9221/AD9223/AD9220 sampling rate,
the selected op amp, and the particular application.
In most
applications, a 30
to 50
resistor is sufficient.
However, some
applications may require a larger resistor value to reduce the
noise bandwidth or possibly limit the fault current in an over-
voltage condition. Other applications may require a larger
resistor value as part of an antialiasing filter. In any case, since
the THD performance is dependent on the series resistance
and the above mentioned factors, optimizing this resistor value
for a given application is encouraged.
A slight improvement in SNR performance and dc offset
performance is achieved by matching the input resistance of
VINA and VINB. The degree of improvement is dependent on
the resistor value and the sampling rate. For series resistor
values greater than 100
, the use of a matching resistor is
encouraged.
Figure 34 shows a plot for THD performance vs. R
SERIES
for
the AD9221/AD9223/AD9220 at their respective sampling rate
and Nyquist frequency. The Nyquist frequency typically repre-
sents the worst case scenario for an ADC. In this case, a high
speed, high performance amplifier (AD8047) was used as the
buffer op amp. Although not shown, the AD9221/AD9223/
AD9220 exhibits a slight increase in SNR (i.e. 1 dB to 1.5 dB)
as the resistance is increased from 0 k
to 2.56 k
due to its
bandlimiting effect on wideband noise. Conversely, it exhibits
slight decrease in SNR (i.e., 0.5 dB to 2 dB) if VINA and
VINB do not have a matched input resistance.
R
SERIES
–
V
–45
–55
–851
10k
10
T
100
1k
–65
–75
AD9220
AD9223
AD9221
Figure 34. THD vs. R
SERIES
(f
IN
= F
S
/2, A
IN
= –0.5 dB, Input
Span = 2 V p-p, V
CM
= 2.5 V)
Figure 34 shows that a small R
SERIES
between 30
and 50
provides the optimum THD performance for the AD9220.
Lower values of R
SERIES
are acceptable for the AD9223 and
AD9221 as their lower sampling rates provide a longer transient
recovery period for the AD8047. Note that op amps with lower
bandwidths will typically have a longer transient recovery
period and hence require a slightly higher value of R
SERIES
and/or lower sampling rate to achieve the optimum THD
performance.
As the value of R
SERIES
increases, a corresponding increase in
distortion is noted. This is due to its interaction with the SHA’s
parasitic capacitor, C
PAR,
which has a signal dependency. Hence,
the resulting R-C time constant is signal dependent and conse-
quently a source of distortion.
The noise or small-signal bandwidth of the AD9221/AD9223/
AD9220 is the same as their full-power bandwidth as shown in
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