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参数资料
| 型号： | AD9223AR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | MS-013AE, SOIC-28 |
| 文件页数： | 15/28页 |
| 文件大小： | 350K |
| 代理商： | AD9223AR |
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AD9221/AD9223/AD9220
REV. D
–15–
If the application requires the largest input span (i.e., 0 V to
5 V) of the AD9221/AD9223/AD9220, the op amp will require
larger supplies to drive it. Various high speed amplifiers in the
Op Amp Selection Guide of this data sheet can be selected to
accommodate a wide range of supply options. Once again,
clamping the output of the amplifier should be considered for
these applications.
Two dc coupled op amp circuits using a noninverting and invert-
ing topology are discussed below. Although not shown, the
noninverting and inverting topologies can be easily configured
as part of an antialiasing filter by using a Sallen-Key or Multiple-
Feedback topology, respectively. An additional R-C network
can be inserted between the op amp’s output and the AD9221/
AD9223/AD9220 input to provide a real pole.
Simple Op Amp Buffer
In the simplest case, the input signal to the AD9221/AD9223/
AD9220 will already be biased at levels in accordance with the
selected input range. It is simply necessary to provide an ad-
equately low source impedance for the VINA and VINB analog
input pins of the A/D. Figure 39 shows the recommended
configuration for a single-ended drive using an op amp. In this
case, the op amp is shown in a noninverting unity gain configu-
ration driving the VINA pin. The internal reference drives the
VINB pin. Note that the addition of a small series resistor of
30
to 50
connected to VINA and VINB will be beneficial
in nearly all cases. Refer to Analog Input Operation section for
a discussion on resistor selection. Figure 39 shows the proper
connection for a 0 V to 5 V input range. Alternative single-
ended input ranges of 0 V to 2
×
VREF can also be realized
with the proper configuration of VREF (refer to the Using the
Internal Reference section).
10
m
F
VINA
VINB
SENSE
AD9221/
AD9223/
AD9220
0.1
m
F
R
S
+V
–V
R
S
VREF
5V
0V
2.5V
U1
Figure 39. Single-Ended AD9221/AD9223/AD9220
Op Amp Drive Circuit
Op Amp with DC Level Shifting
Figure 40 shows a dc-coupled level shifting circuit employing
an op amp, A1, to sum the input signal with the desired dc
offset. Configuring the op amp in the inverting mode with the
given resistor values results in an ac signal gain of –1. If the
signal inversion is undesirable, interchange the VINA and
VINB connections to reestablish the original signal polarity.
The dc voltage at VREF sets the common-mode voltage of the
AD9221/AD9223/AD9220. For example, when VREF = 2.5 V,
the output level from the op amp will also be centered around
2.5 V. The use of ratio matched, thin-film resistor networks will
minimize gain and offset errors. Also, an optional pull-up
resistor, R
P
, may be used to reduce the output load on VREF
to
±
1 mA.
0V
DC
+VREF
–VREF
VINA
VINB
0.1
m
F
500
V
*
0.1
m
F
500
V
*
7
1
2
3
4
5
A1
6
NC
NC
+V
CC
500
V
*
R
S
VREF
500
V
*
R
S
R
P
**
AVDD
*OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D
**OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE
AD9221/
AD9223/
AD9220
Figure 40. Single-Ended Input With DC-Coupled Level Shift
AC COUPLING AND INTERFACE ISSUES
For applications where ac coupling is appropriate, the op amp’s
output can be easily level shifted to the common-mode voltage,
V
CM
, of the AD9221/AD9223/AD9220 via a coupling capaci-
tor. This has the advantage of allowing the op amps common-
mode level to be symmetrically biased to its midsupply level
(i.e. (V
CC
+ V
EE
)/2). Op amps which operate symmetrically
with respect to their power supplies typically provide the best ac
performance as well as greatest input/output span. Hence,
various high speed/performance amplifiers which are restricted
to +5 V/–5 V operation and/or specified for +5 V single-supply
operation can be easily configured for the 5 V or 2 V input span
of the AD9221/AD9223/AD9220. The best ac distortion per-
formance is achieved when the A/D is configured for a 2 V
input span and common-mode voltage of 2.5 V. Note that
differential transformer coupling, which is another form of ac
coupling, should be considered for optimum ac performance.
Simple AC Interface
Figure 41 shows a typical example of an ac-coupled, single-
ended configuration. The bias voltage shifts the bipolar,
ground-referenced input signal to approximately VREF. The
value for C1 and C2
will depend on the size of the resistor, R.
The capacitors, C1 and C2, are typically a 0.1
μ
F ceramic and
10
μ
F tantalum capacitor in parallel to achieve a low cutoff
frequency while maintaining a low impedance over a wide fre-
quency range. The combination of the capacitor and the resistor
form a high-pass filter with a high-pass –3 dB frequency deter-
mined by the equation,
f
–3
dB
= 1/(2
×
π
×
R
×
(
C
1 +
C
2))
The low impedance VREF voltage source biases both the VINB
input and provides the bias voltage for the VINA input. Figure
41 shows the VREF configured for 2.5 V thus the input range
C2
VINA
VINB
SENSE
C1
R
+5V
–5V
R
S
VREF
+VREF
0V
–VREF
V
IN
C2
C1
R
S
AD9221/
AD9223/
AD9220
Figure 41. AC-Coupled Input
of the A/D is 0 V to 5 V. Other input ranges could be selected
by changing VREF but the A/D’s distortion performance will
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9223AR-REEL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 12-bit Parallel 28-Pin SOIC W T/R |
| AD9223ARS | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 12-bit Parallel 28-Pin SSOP 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD9223ARS-REEL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 12-bit Parallel 28-Pin SSOP T/R |
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