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参数资料
| 型号： | AD9225AR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | Complete 12-Bit, 25 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | MS-013AE, SOIC-28 |
| 文件页数： | 18/24页 |
| 文件大小： | 321K |
| 代理商： | AD9225AR |
AD9225
–18–
REV. A
Table V. Out-of-Range Truth Table
OTR
0
0
1
1
MSB
0
1
0
1
Analog Input Is
In Range
In Range
Underrange
Overrange
OVER = “1”
UNDER = “1”
MSB
OTR
MSB
Figure 32. Overrange or Underrange Logic
Digital Output Driver Considerations (DRVDD)
The AD9225 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3V
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families. However,
large drive currents tend to cause glitches on the supplies and
may affect SINAD performance. Applications requiring the
ADC to drive large capacitive loads or large fanout may require
additional decoupling capacitors on DRVDD. In extreme cases,
external buffers or latches may be required.
Clock Input and Considerations
The AD9225 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulsewidth
high and low (t
CH
and t
CL
) specifications for the given A/D as
defined in the Switching Specifications at the beginning of the
data sheet to meet the rated performance specifications. For
example, the clock input to the AD9225 operating at 25 MSPS
may have a duty cycle between 45% to 55% to meet this timing
requirement since the minimum specified t
CH
and t
CL
is 18 ns.
For low clock rates, the duty cycle may deviate from this range
to the extent that both t
CH
and t
CL
are satisfied.
All high speed high resolution A/Ds are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
IN
) due to only aperture jitter (t
A
) can be cal-
culated with the following equation:
SNR
=
20 log
10
1
2
π
f
IN
t
A
In the equation, the rms aperture jitter,
t
A
, represents the root-
sum square of all the jitter sources which include the clock in-
put, analog input signal, and A/D aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
Clock input should be treated as an analog signal in cases where
aperture jitter may affect the dynamic range of the AD9225.
Power supplies for clock drivers should be separated from the
A/D output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other method), it should
be retimed by the original clock at the last step.
The clock input is referred to as the analog supply. Its logic
threshold is AVDD/2. If the clock is being generated by 3 V
logic, it will have to be level shifted into 5 V CMOS logic levels.
This can also be accomplished by ac-coupling and level-shifting
the clock signal.
The AD9225 has a clock tolerance of 5% at 25 MHz. One way
to obtain a 50% duty cycle clock is to divide down a clock of
higher frequency, as shown in Figure 33. This configuration will
also decrease the jitter of the source clock.
+5V
R
D
Q
Q
S
+5V
50MHz
25MHz
Figure 33. Divide-by-Two Clock Circuit
In this case a 50 MHz clock is divided by two to produce the
25 MHz clock input for the AD9225. In this configuration, the
duty cycle of the 50 MHz clock is irrelevant.
The input circuitry for the CLOCK pin is designed to accom-
modate CMOS inputs. The quality of the logic input, particu-
larly the rising edge, is critical in realizing the best possible jitter
performance of the part: the faster the rising edge, the better the
jitter performance.
As a result, careful selection of the logic family for the clock
driver, as well as the fanout and capacitive load on the clock
line, is important. Jitter-induced errors become more predomi-
nant at higher frequency, large amplitude inputs, where the
input slew rate is greatest.
Most of the power dissipated by the AD9225 is from the analog
power supplies. However, lower clock speeds will reduce digital
current. Figure 34 shows the relationship between power and
clock rate.
SAMPLE RATE
380
360
340
320
300
0
35
5
P
10
15
280
260
240
220
200
180
30
20
25
2V
INTERNAL
REFERENCE
1V
INTERNAL
REFERENCE
Figure 34. Power Consumption vs. Clock Rate
Direct IF Down Conversion Using the AD9225
Sampling IF signals above an ADC’s baseband region (i.e., dc
to F
S
/2) is becoming increasingly popular in communication
applications. This process is often referred to as Direct IF Down
Conversion or Undersampling. There are several potential ben-
efits in using the ADC to alias (i.e., or mix) down a narrowband
or wideband IF signal. First and foremost is the elimination of a
complete mixer stage with its associated baseband amplifiers
and filters, reducing cost and power dissipation. Second is the
ability to apply various DSP techniques to perform such func-
tions as filtering, channel selection, quadrature demodulation,
data reduction, detection, etc. A detailed discussion on using
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| AD9225ARRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 25Msps 12-bit Parallel 28-Pin SOIC W T/R |
| AD9225ARS | 功能描述:IC ADC 12BIT 25MSPS 28-SSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9225ARSRL | 功能描述:IC ADC 12BIT 25MSPS 28-SSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
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| AD9225ARSZ | 制造商:Analog Devices 功能描述:IC 制造商:Analog Devices 功能描述:IC, ADC, 12BIT, 25MSPS, SSOP-28 |
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