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参数资料
型号： AD9238BSTZRL-65
厂商： Analog Devices Inc
文件页数： 48/48页
文件大小： 0K
描述： IC ADC 12BIT DUAL 65MSPS 64LQFP
标准包装： 2,000
位数： 12
采样率（每秒）： 65M
数据接口： 并联
转换器数目： 2
功率耗散（最大）： 600mW
电压电源： 单电源
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（7x7）
包装： 带卷 (TR)
输入数目和类型： 4 个单端，单极；2 个差分，单极
AD9238
Rev. C | Page 9 of 48
Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4, 13, 16
AGND
Analog Ground.
2
VIN+_A
Analog Input Pin (+) for Channel A.
3
VIN–_A
Analog Input Pin () for Channel A.
5, 12, 17, 64
AVDD
Analog Power Supply.
6
REFT_A
Differential Reference (+) for Channel A.
7
REFB_A
Differential Reference () for Channel A.
8
VREF
Voltage Reference Input/Output.
9
SENSE
Reference Mode Selection.
10
REFB_B
Differential Reference () for Channel B.
11
REFT_B
Differential Reference (+) for Channel B.
14
VIN_B
Analog Input Pin () for Channel B.
15
VIN+_B
Analog Input Pin (+) for Channel B.
18
CLK_B
Clock Input Pin for Channel B.
19
DCS
Enable Duty Cycle Stabilizer (DCS) Mode (Tie High to Enable).
20
DFS
Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement).
21
PDWN_B
Power-Down Function Selection for Channel B:
Logic 0 enables Channel B.
Logic 1 powers down Channel B. (Outputs static, not High-Z.)
22
OEB_B
Output Enable Bit for Channel B:
Logic 0 enables Data Bus B.
Logic 1 sets outputs to High-Z.
23, 24, 42, 43
DNC
Do Not Connect Pins. Should be left floating.
25 to 27,
30 to 38
D0_B (LSB) to
D11_B (MSB)
Channel B Data Output Bits.
28, 40, 53
DRGND
Digital Output Ground.
29, 41, 52
DRVDD
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF.
39
OTR_B
Out-of-Range Indicator for Channel B.
44 to 51,
54 to 57
D0_A (LSB) to
D11_A (MSB)
Channel A Data Output Bits.
58
OTR_A
Out-of-Range Indicator for Channel A.
59
OEB_A
Output Enable Bit for Channel A:
Logic 0 enables Data Bus A.
Logic 1 sets outputs to High-Z.
60
PDWN_A
Power-Down Function Selection for Channel A:
Logic 0 enables Channel A.
Logic 1 powers down Channel A. (Outputs static, not High-Z.)
61
MUX_SELECT
Data Multiplexed Mode. (See Data Format section for how to enable; high setting disables
output data multiplexed mode).
62
SHARED_REF
Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared
Reference Mode).
63
CLK_A
Clock Input Pin for Channel A.
EP
For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.
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