参数资料
型号: AD9276-65EBZ
厂商: Analog Devices Inc
文件页数: 47/48页
文件大小: 0K
描述: BOARD EVALUATION FOR AD9276
设计资源: AD9276/77 Eval Brd Gerber Files
标准包装: 1
ADC 的数量: 1
位数: 12
采样率(每秒): 65M
数据接口: 串行,SPI?
输入范围: 733 mVpp
在以下条件下的电源(标准): 195mW @ 40MSPS
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD9276
已供物品:
AD9276
Rev. 0 | Page 8 of 48
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 3.
Parameter1
Temperature
Min
Typ
Max
Unit
Clock Rate
40 MSPS (Mode I)
Full
10
40
MHz
65 MSPS (Mode II)
Full
10
65
MHz
80 MSPS (Mode III)
Full
10
80
MHz
Clock Pulse Width High (tEH)
Full
6.25
ns
Clock Pulse Width Low (tEL)
Full
6.25
ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
(tSAMPLE/2) + 3.1
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO Propagation Delay (tFCO)
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
(tSAMPLE/2) + 3.1
ns
DCO Propagation Delay (tCPD)4
Full
tFCO + (tSAMPLE/24)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/24) 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/24) 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
Data-to-Data Skew (tDATA-MAX tDATA-MIN)
Full
±100
±350
ps
Wake-Up Time (Standby), GAIN+ = 0.5 V
25°C
2
μs
Wake-Up Time (Power-Down)
25°C
1
ms
Pipeline Latency
Full
8
Clock
cycles
APERTURE
Aperture Uncertainty (Jitter)
25°C
<1
ps rms
LO GENERATION
4LO Frequency
Full
4
40
MHz
LO Divider RESET Setup Time5
Full
5
ns
LO Divider RESET Hold Time5
Full
5
ns
LO Divider RESET High Pulse Width
Full
20
ns
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Can be adjusted via the SPI.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
5 RESET edge to rising 4LO edge.
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