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参数资料
| 型号： | AD9284BCPZ-250 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT 250MSPS 1.8V 48LFCSP |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 250M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 330mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个差分，双极 |
| 配用： | AD9284-250EBZ-ND - BOARD EVAL FOR AD9284 |
AD9284
Data Sheet
Rev. A | Page 22 of 24
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9284 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements that are needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9284, it is strongly recom-
mended that two separate supplies be used. Use one 1.8 V
supply for analog (AVDD); use a separate 1.8 V supply for the
digital output supply (DRVDD). If a common 1.8 V AVDD and
DRVDD supply must be used, the AVDD and DRVDD domains
must be isolated with a ferrite bead or filter choke and separate
decoupling capacitors. Several different decoupling capacitors
can be used to cover both high and low frequencies. Locate these
capacitors close to the point of entry at the printed circuit board
(PCB) level and close to the pins of the part, with minimal
trace length.
A single PCB ground plane should be sufficient when using the
AD9284. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
Exposed Paddle Thermal Heat Sink Recommendations
The exposed paddle (Pin 0) is the only ground connection
for the AD9284; therefore, it must be connected to analog
ground (AGND) on the customer PCB. To achieve the best
electrical and thermal performance, mate an exposed (no
solder mask), continuous copper plane on the PCB to the
AD9284 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the
lowest possible resistive thermal path for heat dissipation to
flow through the bottom of the PCB. Fill or plug these vias
with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), at www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor.
RBIAS
The AD9284 requires that a 10 k resistor be placed between
the RBIAS pin and ground. This resistor, which sets the master
current reference of the ADC core, should have at least a 1%
tolerance.
Reference Decoupling
Decouple the VREF pin externally to ground with a low ESR,
1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic
capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9284 to prevent these signals from transitioning at the converter
inputs during critical sampling periods.
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