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参数资料
| 型号： | AD9518-0ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/64页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 6CH 2.8GHZ 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.95GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
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Data Sheet
AD9518-0
Rev. C | Page 25 of 64
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
REF1
REF2
AD9518-1
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_ SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
RE
N
CE
HOLD
OUT0
OUT1
OUT0
OUT1
LVPECL
DIVIDE BY
1 TO 32
OUT2
OUT3
OUT2
OUT3
LVPECL
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
0
1
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
DIVIDE BY
2, 3, 4, 5, OR 6
06
43
0-
02
8
OUT4
OUT5
OUT4
OUT5
LVPECL
Figure 30. Clock Distribution or External VCO < 1600 MHz
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is less than 1600 MHz, a configuration that bypasses
the VCO divider can be used. This configuration differs from the
1600 MHz section only in that the VCO divider (divide-by-2/
divide-by-3/divide-by-4/divide-by-5/divide-by-6) is bypassed.
This limits the frequency of the clock source to <1600 MHz (due
to the maximum input frequency allowed at the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
less than 1600 MHz, use the register settings shown in Table 24.
Table 24. Settings for Clock Distribution < 1600 MHz
Register
Function
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off )
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
0x1E1[1] = 0b
CLK selected as the source
When using the internal PLL with an external VCO of <1600 MHz,
the PLL must be turned on.
Table 25. Settings for Using Internal PLL with External VCO <
1600 MHz
Register
Function
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
0x010[1:0] = 00b
PLL normal operation (PLL on), along with
other appropriate PLL settings in Register 0x010
to Register 0x01D
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 26. Setting the PFD Polarity
Register
Function
0x010[7] = 0b
PFD polarity positive (higher control voltage
produces higher frequency)
0x010[7] = 1b
PFD polarity negative (higher control voltage
produces lower frequency)
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9518-0ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 2.8GHZ 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9518-0A-PCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:6-Output Clock Generator |
| AD9518-0BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray |
| AD9518-0BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9518-1 | 制造商:AD 制造商全称:Analog Devices 功能描述:6-Output Clock Generator with Integrated 2.5 GHz VCO |
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