参数资料
型号: AD9518-2ABCPZ-RL7
厂商: Analog Devices Inc
文件页数: 49/64页
文件大小: 0K
描述: IC CLOCK GEN 6CH 2.2GHZ 48LFCSP
标准包装: 750
类型: 时钟发生器,扇出配送
PLL:
输入: CMOS,LVDS,LVPECL
输出: LVPECL
电路数: 1
比率 - 输入:输出: 1:6
差分 - 输入:输出: 是/是
频率 - 最大: 2.33GHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 带卷 (TR)
Data Sheet
AD9518-2
Rev. C | Page 53 of 64
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01C
7
Disable switchover
deglitch
Disables or enables the switchover deglitch circuit.
0: enables switchover deglitch circuit (default).
1: disables switchover deglitch circuit.
6
Select REF2
If Register 0x01C, Bit 5 = 0b; selects reference for PLL.
0: selects REF1 (default).
1: selects REF2.
5
Use REF_SEL pin
Sets method of PLL reference selection.
0: uses Register 0x01C, Bit 6 (default).
1: uses REF_SEL pin.
[4:3]
Reserved
Reserved (default: 00b).
2
REF2 power-on
This bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
1
REF1 power-on
This bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
0
Differential
reference
Selects the PLL reference mode: differential or single-ended. Single-ended must be selected for the automatic
switchover between REF1 and REF2 to work.
0: single-ended reference mode (default).
1: differential reference mode.
0x01D
4
PLL status register
disable
Disables the PLL status register readback.
0: PLL status register enable (default).
1: PLL status register disable.
3
LD pin comparator
enable
Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When
in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if
the PLL was previously in a locked state (see Figure 38). Otherwise, this function can be used with the REFMON and
STATUS pins to monitor the voltage on this pin.
0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default).
1: enables LD pin comparator.
2
Holdover enable
Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
1
External holdover
control
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
0: automatic holdover mode; holdover controlled by automatic holdover circuit (default).
1: external holdover mode; holdover controlled by SYNC pin.
0
Holdover enable
Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
0x01F
6
VCO cal finished
Read-only register. Indicates status of the VCO calibration.
0: VCO calibration not finished.
1: VCO calibration finished.
5
Holdover active
Read-only register. Indicates if the part is in the holdover state (see Figure 38). This is not the same as holdover enabled.
0: not in holdover.
1: holdover state active.
4
REF2 selected
Read-only register. Indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
3
VCO frequency >
threshold
Read-only register. Indicates if the VCO frequency is greater than the threshold (see Table 15: REF1, REF2, and VCO
frequency status monitor).
0: VCO frequency is less than the threshold.
1: VCO frequency is greater than the threshold.
2
REF2 frequency >
threshold
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x1A, Bit 6.
0: REF2 frequency is less than threshold frequency.
1: REF2 frequency is greater than threshold frequency.
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