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| 型号： | AD9518-2ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/64页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 6CH 2.2GHZ 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.33GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
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Data Sheet
AD9518-2
Rev. C | Page 11 of 64
LD, STATUS, AND REFMON PINS
Table 15.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see Table 44, Register 0x017, Register 0x01A, and
Register 0x01B
Output Voltage High (VOH)
2.7
V
Output Voltage Low (VOL)
0.4
V
MAXIMUM TOGGLE RATE
100
MHz
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs may
couple to output when any of these pins are toggling
ANALOG LOCK DETECT
Capacitance
3
pF
On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
1.02
MHz
Frequency above which the monitor always indicates the
presence of the reference
Extended Range (REF1 and REF2 Only)
8
kHz
Frequency above which the monitor always indicates the
presence of the reference
LD PIN COMPARATOR
Trip Point
1.6
V
Hysteresis
260
mV
POWER DISSIPATION
Table 16.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER DISSIPATION, CHIP
Power-On Default
0.76
1.0
W
No clock; no programming; default register values;
does not include power dissipated in external resistors
Full Operation
1.1
1.7
W
PLL on; internal VCO = 2335 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 584 MHz;
does not include power dissipated in external resistors
PD Power-Down
75
185
mW
PD pin pulled low; does not include power dissipated
in terminations
PD Power-Down, Maximum Sleep
31
mW
PD pin pulled low; PLL power-down, Register 0x010[1:0] =
01b; SYNC power-down, Register 0x230[2] = 1b; REF for
distribution power-down, Register 0x230[1] = 1b
VCP Supply
4
4.8
mW
PLL operating; typical closed-loop configuration
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power delta when a function is enabled/disabled
VCO Divider
30
mW
VCO divider bypassed
REFIN (Differential)
20
mW
All references off to differential reference enabled
REF1, REF2 (Single-Ended)
4
mW
All references off to REF1 or REF2 enabled; differential
reference not enabled
VCO
70
mW
CLK input selected to VCO selected
PLL
75
mW
PLL off to PLL on, normal operation; no reference
enabled
Channel Divider
30
mW
Divider bypassed to divide-by-2 to divide-by-32
LVPECL Channel (Divider Plus Output Driver)
160
mW
No LVPECL output on to one LVPECL output on,
independent of frequency
LVPECL Driver
90
mW
Second LVPECL output turned on, same channel
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9518-2ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 2.2GHZ 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9518-2A-PCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:6-Output Clock Generator with Integrated 2.2 GHz VCO |
| AD9518-2BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray |
| AD9518-2BCPZ-REEL7 | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AD9518-3 | 制造商:AD 制造商全称:Analog Devices 功能描述:6-Output Clock Generator with 6-Output Clock Generator with |
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