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参数资料
| 型号： | AD9520-4BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 配用： | AD9520-4/PCBZ-ND - BOARD EVAL FOR AD9520-4 |
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AD9520-4
Data Sheet
Rev. A | Page 44 of 80
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 15 input clock cycles. For example, if
the frequency at the input of the channel divider is 1 GHz, the
channel divider output can be delayed by up to 15 ns. The
divider outputs can also be set to start high or to start low.
Operation Modes
There are three clock distribution operating modes, and these
are shown in Figure 50. One of these modes uses the internal
VCO, whereas the other two modes bypass the internal VCO
and use the signal provided on the CLK/CLK pins.
In Mode 0 (internal VCO mode), there are two signal paths
available. In the first path, the VCO signal is sent to the VCO
divider and then to the individual channel dividers. In the
second path, the user bypasses the VCO and channel dividers
and sends the VCO signal directly to the drivers.
When CLK is selected as the source, it is not necessary to use the
VCO divider if the CLK frequency is less than the maximum
channel divider input frequency (1600 MHz); otherwise, the
VCO divider must be used to reduce the frequency going to
the channel dividers.
Table 32 shows how the VCO, CLK, and VCO divider are selected.
Register 0x1E1[1:0] selects the channel divider source and
determines whether the VCO divider is used. It is not possible
to select the VCO without using the VCO divider.
Table 32. Operation Modes
Mode
Register 0x1E1
Channel Divider Source
VCO Divider
Bit 1
Bit 0
2
0
CLK
Used
1
0
1
CLK
Not used
0
1
0
VCO
Used
1
Not allowed
CLK or VCO Direct-to-LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs. This configuration can pass frequencies
up to the maximum frequency of the VCO directly to the LVPECL
outputs. However, the LVPECL outputs may not be able to meet
Either the internal VCO or the CLK can be selected as the source
for the direct-to-output signal routing. To connect the LVPECL
outputs directly to the internal VCO or CLK, the VCO divider
must be selected as the source to the distribution section, even
if no channel uses it.
Table 33. Routing VCO Divider Input Directly to the Outputs
Register Setting
Selection
0x1E1[1:0] = 00b
CLK is the source; VCO divider selected
0x1E1[1:0] = 10b
VCO is the source; VCO divider selected
0x192[1] = 1b
Direct-to-output OUT0, OUT1, OUT2
0x195[1] = 1b
Direct-to-output OUT3, OUT4, OUT5
0x198[1] = 1b
Direct-to-output OUT6, OUT7, OUT8
0x19B[1] = 1b
Direct-to-output OUT9, OUT10, OUT11
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (1, 2, 3, 4, 5, and 6)
and the division of the channel divider. Table 34 shows how the
frequency division for a channel is set.
Table 34. Frequency Division
CLK or VCO
Selected
VCO
Divider
Setting1
Channel
Divider
Setting
Direct to
Output
Setting
Resulting
Frequency
Division
CLK or VCO
input
1 to 6
Don’t
care
Enable
1
CLK or VCO
input
1 to 6
2 to 32
Disable
(1 to 6) ×
(2 to 32)
CLK or VCO
input
2 to 6
Bypass
Disable
(2 to 6) × (1)
CLK or VCO
input
1
Bypass
Disable
Output static
(illegal state)
CLK (internal
VCO off)
VCO divider
bypassed
Bypass
Don’t
care
1
CLK (internal
VCO off)
VCO divider
bypassed
2 to 32
Don’t
care
2 to 32
1
The bypass VCO divider (Register 0x1E1[0] = 1b) is not the same as VCO
divider = 1 (divide-by-1).
MODE 0 (INTERNAL VCO MODE)
CLK
LF
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLOCK
DISTRI-
BUTION
PLL
DISTRIBUTION
CLOCK
MODE 1 (CLOCK DISTRIBUTION MODE)
DISTRIBUTION
CLOCK
MODE 2 (HF CLOCK DISTRIBUTION MODE)
CLK
LF
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLOCK
DISTRI-
BUTION
PLL
CLK
LF
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLOCK
DISTRI-
BUTION
PLL
DISTRIBUTION
CLOCK
07217-
054
Figure 50. Simplified Diagram of the Three Clock Distribution Operation Modes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-5 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator |
| AD9520-5/PCBZ | 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9520-5BCPZ | 功能描述:IC CLOCK GEN EXT VCO 64-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| AD9520-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9521JH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Log/Antilog Amplifier |
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