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| 型号： | AD9572ACPZLVD-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 40LFCSP |
| 标准包装： | 2,500 |
| 类型： | 时钟发生器，扇出配送，多路复用器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:7 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 156.25MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.97 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-WQ（6x6） |
| 包装： | 带卷 (TR) |
AD9572
Rev. B | Page 17 of 20
Table 15. FREQSEL (Pin 27) Definition
FREQSEL
Frequency Available
from Pin 19 and Pin 20
(MHZ)
Frequency Available
from Pin 21 and Pin 22
(MHZ)
0
125
1
100
NC
125
100
The simplified equivalent circuits of the LVDS and LVPECL
outputs are shown in Figure 18 and Figure 19.
3.5mA
OUT
OUTB
07
49
8-
01
4
Figure 18. LVDS Output Simplified Equivalent Circuit
3.3V
OUT
OUTB
GND
07
49
8-
01
5
Figure 19. LVPECL Output Simplified Equivalent Circuit
The differential outputs are factory programmed to either LVPECL
or LVDS format, and either option can be sampled on request.
CMOS drivers tend to generate more noise than differential
outputs and, as a result, the proximity of the 33.33 MHz output
to Pin 21 and Pin 22 does affect the jitter performance when
FREQSEL = 0 (that is, when the differential output is generating
125 MHz). For this reason, the 33 MHz pin can be forced to a
low state by asserting the FORCE_LOW signal on Pin 37 (see
Table 16). An internal pull-down enables the 33.33 MHz output
if the pin is not connected.
Table 16. FORCE_LOW (Pin 37) Definition
FORCE_LOW
33.33 MHz Output (Pin 23)
0 or NC
33.33 MHz
1
0
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the reference clock and feedback
divider to produce an output proportional to the phase and
frequency difference between them. Figure 20 shows a
simplified schematic.
0
749
8-
0
16
D1 Q1
CLR1
REFCLK
HIGH
UP
D2 Q2
CLR2
HIGH
DOWN
CP
CHARGE
PUMP
3.3V
GND
FEEDBACK
DIVIDER
Figure 20. PFD Simplified Schematic
POWER SUPPLY
The AD9572 requires a 3.3 V ± 10% power supply for VS. The
tables in the Specifications section give the performance expected
from the AD9572 with the power supply voltage within this
range. The absolute maximum range of 0.3 V to +3.6 V, with
respect to GND, must never be exceeded on the VS pin.
Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9572 should be bypassed with
adequate capacitors (0.1 μF) at all power pins as close as
possible to the part. The layout of the AD9572 evaluation board
is a good example.
The exposed metal paddle on the AD9572 package is an electrical
connection, as well as a thermal enhancement. For the device to
function properly, the paddle must be properly attached to ground
(GND). The PCB acts as a heat sink for the AD9572; therefore,
this GND connection should provide a good thermal path to a
larger dissipation area, such as a ground plane on the PCB.
CMOS CLOCK DISTRIBUTION
The AD9572 provides two CMOS clock outputs (one 25 MHz
and one 33.33 MHz) that are dedicated CMOS levels. Whenever
single-ended CMOS clocking is used, some of the following
general guidelines should be followed.
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. CMOS outputs are limited
in terms of the capacitive load or trace length that they can drive.
Typically, trace lengths less than 6 inches are recommended to
preserve signal rise/fall times and signal integrity.
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9572 do not supply enough current
to provide a full voltage swing with a low impedance resistive,
far-end termination, as shown in Figure 21. The far-end
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