参数资料
型号: AD9572ACPZPEC
厂商: Analog Devices Inc
文件页数: 11/20页
文件大小: 0K
描述: IC PLL CLOCK GEN 25MHZ 40LFCSP
标准包装: 1
类型: 时钟发生器,扇出配送,多路复用器
PLL:
输入: 晶体
输出: CMOS,LVDS,LVPECL
电路数: 1
比率 - 输入:输出: 1:7
差分 - 输入:输出: 无/是
频率 - 最大: 156.25MHz
除法器/乘法器: 是/无
电源电压: 2.97 V ~ 3.63 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-WQ(6x6)
包装: 托盘
产品目录页面: 776 (CN2011-ZH PDF)
AD9572
Rev. B | Page 19 of 20
sine wave or square wave, provided that an external divider is
used to bias the input at VS/2.
Table 17. REFSEL (Pin 9) Definition
REFSEL
Reference Source
0
REFCLK input
1
Internal crystal oscillator
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as important
as the circuit design. Proper RF techniques must be used for
device selection, placement, and routing, as well as for power
supply bypassing and grounding to ensure optimum performance.
Each power supply pin should have independent decoupling and
connections to the power supply plane. It is recommended that the
device exposed paddle be directly connected to the ground plane
by a grid of at least nine vias. Care should be taken to ensure that
the output traces cannot couple onto the reference or crystal input
circuitry. Traces should not be routed under the crystal. Output
signal traces should be kept on the top PCB layer; these traces have
very high edge rates, and the use of PCB vias will result in signal
integrity problems.
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