参数资料
| 型号： | AD9573ARUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/12页 |
| 文件大小： | 0K |
| 描述： | IC PCI CLCOK GEN 25MHZ 16TSSOP |
| 标准包装： | 96 |
| 系列： | PCI Express® (PCIe) |
| 类型： | 时钟/频率发生器，扇出缓冲器（分配） |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 输入： | 晶体 |
| 输出： | LVCMOS，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 100MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 托盘 |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
AD9573
Rev. 0 | Page 9 of 12
THEORY OF OPERATION
XTAL
OSC
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
DIVIDE
BY 4
DIVIDE
BY 3
CMOS
33.33MHz
33M
VDDA GNDA
VDD,
VDD33
GND,
GND33
OE
DIVIDE
BY 25
2.5GHz
VCO
LDO
100M
LVDS
100MHz
VLDO
AD9573
07
50
0-
0
1
Figure 8. Detailed Block Diagram
Figure 8 shows a block diagram of the AD9573. The chip
features a PLL core, which is configured to generate the specific
clock frequencies required for PCI-express, without any user
programming. This PLL is based on proven Analog Devices
synthesizer technology, noted for its exceptional phase noise
performance. The AD9573 is highly integrated and includes the
loop filter, a regulator for supply noise immunity, all the
necessary dividers, output buffers, and a crystal oscillator. A
user need only supply a 25 MHz external crystal to implement
an entire PCIe clocking solution, which does not require any
processor intervention.
OUTPUTS
Table 11 provides a summary of the outputs available.
Table 11. Output Formats
Frequency
Format
Copies
100 MHz
LVDS
1
33.33 MHz
LVCMOS
1
The simplified equivalent circuit of the LVDS output is shown
in Figure 9. The 100 MHz output is described as LVDS because
it uses an LVDS driver topology. However, the levels are HCSL
compatible, and therefore do not meet the LVDS standard. The
output current has been increased to provide a larger output
swing than standard LVDS.
6.5mA
OUT
OUTB
07
50
0-
01
2
Figure 9. LVDS Output Simplified Equivalent Circuit
Both outputs can be placed in a high impedance state by
connecting the OE pin according to
. This pin has
a 50 kΩ pull-down resistor.
Table 12. Output Enable Pin Function
OE State
Output State
0
Enabled
1
High impedance
Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the reference clock and feedback
divider to produce an output proportional to the phase and
frequency difference between them. Figure 10 shows a
simplified schematic.
0
75
00
-01
3
D1 Q1
CLR1
REFCLK
HIGH
UP
D2 Q2
CLR2
HIGH
DOWN
CP
CHARGE
PUMP
3.3V
GND
FEEDBACK
DIVIDER
Figure 10. PFD Simplified Schematic and Timing (in Lock)
POWER SUPPLY
The AD9573 requires a 3.3 V ± 10% power supply for VDD.
The tables in the Specifications section give the performance
expected from the AD9573 with the power supply voltage
within this range. The absolute maximum range of (0.3 V)
(+3.6 V), with respect to GND, must never be exceeded on
the VDD or VDDA pins.
Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9573 should be decoupled with
adequate capacitors (0.1 μF) at all power pins as close as
possible to these power pins. The layout of the AD9573
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